• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2013.05a
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• pp.97-97
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• 2013

We present a comprehensive study on the integration of h-BN with silicon MOSFET. Temperature dependent mobility modeling is used to discern the effects of top-gate dielectric on carrier transport and identify limiting factors of the system. The result indicates that coulomb scattering and surface roughness scattering are the dominant scattering mechanisms for silicon MOSFETs at relatively low temperature. Interposing a layer of h-BN between $SiO_2$ and Si effectively weakens coulomb scattering by separating carriers in the silicon inversion layer from the charged centers as 2-dimensional h-BN is relatively inert and is expected to be free of dangling bonds or surface charge traps owing to the strong, in-plane, ionic bonding of the planar hexagonal lattice structure, thus leading to a significant improvement in mobility relative to undecorated system. Furthermore, the atomically planar surface of h-BN also suppresses surface roughness scattering in this Si MOSFET system, resulting in a monotonously increasing mobility curve along with gate voltage, which is different from the traditional one with a extremum in a certain voltage. Alternatively, high-k dielectrics can lead to enhanced transport properties through dielectric screening. Modeling indicates that we can achieve even higher mobility by using h-BN decorated $HfO_2$ as gate dielectric in silicon MOSFETs instead of h-BN decorated $SiO_2$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.104-104
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• 2009

Critical dimensions has rapidly shrunk to increase the degree of integration and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate insulator layer and the low conductivity characteristic of poly-silicon. To cover these faults, the study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$ and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-silicon gate is not compatible with high-k materials for gate-insulator. To integrate high-k gate dielectric materials in nano-scale devices, metal gate electrodes are expected to be used in the future. Currently, metal gate electrode materials like TiN, TaN, and WN are being widely studied for next-generation nano-scale devices. The TaN gate electrode for metal/high-k gate stack is compatible with high-k materials. According to this trend, the study about dry etching technology of the TaN film is needed. In this study, we investigated the etch mechanism of the TaN thin film in an inductively coupled plasma (ICP) system with $O_2/BCl_3/Ar$ gas chemistry. The etch rates and selectivities of TaN thin films were investigated in terms of the gas mixing ratio, the RF power, the DC-bias voltage, and the process pressure. The characteristics of the plasma were estimated using optical emission spectroscopy (OES). The surface reactions after etching were investigated using X-ray photoelectron spectroscopy (XPS) and auger electron spectroscopy (AES).

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.479-479
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• 2011

Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.817-820
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• 2005

The gate-length dependence of maximun oscillation frequency $f_{MAX}$ is modeled by using scaling equations of equivalent-circuit parameters extracted from measured S-parameters of Nano-scale MOSFETs. The accuracy of the modeled $f_{MAX}$ is verified by observing good agreements with measured ones. It is observed that the $f_{MAX}$ initially increases with decreasing $L_g$ and then $f_{MAX}$ becomes saturated from $L_g$ less than 65nm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.275-278
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• 2002

As the gate lengths of MOSFETs are scaled down to sub-50nm regime, there are key issues to be considered in the device design. In this paper, we have investigated the characteristics of threshold voltage for MOSFET device. We have simulated the MOSFETs with gate lengths from 100nm to 30nm using generalized scaling. Then, we have known the device scaling limits for nano structure MOSFET. We have determined the threshold voltages using LE(Linear Extraction) method.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.76-79
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• 2003

The characteristic of single wall carbon nanotube (SW-CNT) and herringbone nano fiber (HB-CNF) emitters was described. SW-CNT synthesized by arc discharge and HB-CNF prepared by thermal CVD were mixed with binders and conductive materials, and then were formed by screen-printing process. In order to obtain efficient field emissions, the surface treatment of rubbing & peel-off was applied to the printed CNT and CNF emitters. The basic structure of FED was of a diode type through fully vacuum packaging. Also, we proposed a new triode type of field emitter using a mesh gate plate having tapered holes and could achieve the ideal triode properties with no gate leakage currents.

• Proceedings of the Korean Vacuum Society Conference
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• 2008.08a
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• pp.144-145
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• 2008

• Advances in nano research
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• v.3 no.1
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• pp.49-54
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• 2015

The structure represents symmetrical metal electrode (gate 1) - front $SiO_2$ layer - n-Si nanowire FET - buried $SiO_2$ layer - metal electrode (gate 2). At the symmetrical gate voltages high conductive regions near the gate 1 - front $SiO_2$ and gate 2 - buried $SiO_2$ interfaces correspondingly, and low conductive region in the central region of the NW are formed. Possibilities of applications of nanosize FETs at the deep inversion and depletion as a distributed capacitance are demonstrated. Capacity density is an order to ${\sim}{\mu}F/cm^2$. The charge density, it distribution and capacity value in the nanowire can be controlled by a small changes in the gate voltages. at the non-symmetrical gate voltages high conductive regions will move to corresponding interfaces and low conductive region will modulate non-symmetrically. In this case source-drain current of the FET will redistributed and change current way. This gives opportunity to investigate surface and bulk transport processes in the nanosize inversion channel.

• Proceedings of the Korean Vacuum Society Conference
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• 2007.08a
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• pp.307-307
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• 2007

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1434-1435
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• 2006

본 연구에서는 polymer gate insulators에 따른 pentacene 유기 박막 트랜지스터 (Organic Thin-Film Transistors)의 전기적 특성을 atom force microscope (AFM), x-ray diffraction (XRD) 그리고 I-V 측정을 이용하여 분석하였다. Pentacene 박막 트랜지스터의 전기적 특성은 pentacene의 증착 조건뿐만 아니라 polymer gate insulator에 따라 크게 영향을 받는다. 따라서 다양한 polymer 기판 위에 온도, 두께 그리고 증착 속도에 따라 pentacene을 증착 하였다. 그리고 증착된 pentacne을 AFM, XRD를 이용하여 pentacene의 구조, 결정화 그리고 grain 크기 등을 분석하였다. 또한 inverted stagger며 구조의 pentacene 박막 트랜지스터 소자를 제작하고 I-V 측정하여 그 결과를 분석하였다.