• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.5
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• pp.955-960
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• 2007

In this paper, the deviation of tunneling current for gate voltage has been investigated in double gate MOSFET developed to decrease the short channel effects. In device scaled to nano units, the tunneling current is very important current factor and rapidly increases,compared with thermionic emission current according to device size scaled down. We consider the change of tunneling current according to gate voltage in this study. The potential distribution is derived to observe the change of tunneling current according to gate voltage, and the deviation of off-current is derived from the relation of potential distribution and tunneling probability. The derived current is compared with the termionic emission current, and the relation of effective gate voltage to decrease tunneling current is obtained.

• International journal of advanced smart convergence
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• v.5 no.3
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• pp.66-71
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• 2016

Smart building gate security control system using smartphone integrated with near field communication (NFC) has become part of daily life usage these days. The technology change in replacing RF NFC device using visible light communication technology based approach growing faster in recent days. This paper propose a design and development of gate security control system using color code based user authentication ID generation as part of an intelligent access control system to control automatic door open and close. In this approach gate security access control use the recent visible light communication technology trends to transfer the user specific authentication code to door access control system using color code on smartphone screen. Using a camera in the door access control system (ACS), color codes on smartphone screens are detected and matched to the database of authenticated user to open the door automatically in gate security system. We measure the visual light communication technology efficiency as a part of the research and the experiments have revealed that more than 95% users authenticated correctly at the suggested experiment environment on gate security control system.

• Journal of the Korean Vacuum Society
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• v.18 no.4
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• pp.302-309
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• 2009

We fabricated a Si nano floating gate memory with Schottky barrier tunneling transistor structure. The device was consisted of Schottky barriers of Er-silicide at source/drain and Si nanoclusters in the gate stack formed by LPCVD-digital gas feeding method. Transistor operations due to the Schottky barrier tunneling were observed under small gate bias < 2V. The nonvolatile memory properties were investigated by measuring the threshold voltage shift along the gate bias voltage and time. We obtained the 10/50 mseconds for write/erase times and the memory window of $\sim5V$ under ${\pm}20\;V$ write/erase voltages. However, the memory window decreased to 0.4V after 104seconds, which was attributed to the Er-related defects in the tunneling oxide layer. Good write/erase endurance was maintained until $10^3$ write/erase times. However, the threshold voltages moved upward, and the memory window became small after more write/erase operations. Defects in the LPCVD control oxide were discussed for the endurance results. The experimental results point to the possibility of a Si nano floating gate memory with Schottky barrier tunneling transistor structure for Si nanoscale nonvolatile memory device.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.21-26
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• 2008

We fabricated nano-particles of ZnO, $In_2O_3$ and $SnO_2$ by using the chemical reaction between metal thin films and polyamic acid. The average size and density of these ZnO, $In_2O_3$ and $SnO_2$ nano-particles was approximately 10, 7, and 15 nm, and $2{\times}10^{11},\;6{\times}10^{11},\;2.4{\times}10^{11}cm^{-2}$, respectively. Then, we fabricated nano-floating gate memory (NFGM) devices with ZnO and $In_2O_3$ nano-particles embedded in the devices' polyimide dielectrics and silicon dioxide layers as control and tunnel oxides, respectively. We measured the current-voltage characteristics, endurance properties and retention times of the memory devices using a semiconductor parameter analyzer. In the $In_2O_3$ NFGM, the threshold voltage shift (${\Delta}V_T$) was approximately 5 V at the initial state of programming and erasing operations. However, the memory window rapidly decreased after 1000 s from 5 to 1.5 V. The ${\Delta}V_T$ of the NFGM containing ZnO was approximately 2 V at the initial state, but the memory window decreased after 1000 s from 2 to 0.4 V. These results mean that metal-oxide nano-particles have feasibility to apply NFGM devices.

• Transactions on Electrical and Electronic Materials
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• v.10 no.2
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• pp.35-39
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• 2009

A novel Helmholtz coil inductively coupled plasma(H-ICP) etcher is proposed and characterized for deep nano-scale CMOS technology. Various hardware tests are performed while varying key parameters such as distance between the top and bottom coils, the distance between the chamber ceiling and the wafer, and the chamber height in order to determine the optimal design of the chamber and optimal process conditions. The uniformity was significantly improved by applying the optimum conditions. The plasma density obtained with the H-ICP source was about $5{\times}10^{11}/cm^3$, and the electron temperature was about 2-3 eV. The etching selectivity for the poly-silicon gate versus the ultra-thin gate oxide was 482:1 at 10 sccm of $HeO_2$. The proposed H-ICP was successfully applied to form multiple 60-nm poly-silicon gate layers.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.248-250
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• 2019

입자가속기는 물질의 미세 구조를 밝히기 위해 기본 입자를 가속, 충돌시키는 장치로 최근 암치료 등 의학적 용도로도 이용되고 있다. 그러나 고속으로 고압을 인가시켜야 하는 장치인 만큼 기존에 명확히 설립된 회로가 없다. 이에 본 논문에서는 Ion gate를 등가회로로 구성하여 Fast Switch 장치의 기본 회로를 제안 및 분석, 실험하였다. 또한 기본 회로에서 발생하는 문제들을 개선하고자 RC Input filter와 기타 파라미터들의 설계와 Fast switch와 Ion gate를 잇는 wire 내의 기생성분을 고찰하였고 Ion gate 구동을 위해 기준이 되는 명확한 Fast switch 회로를 제안한다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.52-58
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• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1501-1502
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• 2011

In this paper, an investigation of the 8" process for Trench Power MOSFET Application and Trench MOSFETs and its impact on device performance is presented. Layout dimensions of trench power MOSFETs have been continuously reduced in order to decrease the specific on-resistance, maintaining equal vertical dimensions. We discuss experimental results for devices with a pitch size down fabricated with an unconventional gate trench topology and a simplified manufacturing scheme. The fabricated Trench MOSFETs are observed the trench gate oxidation by SEM.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1402-1404
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• 2009

The silicon nitride films for gate dielectric were deposited by catalytic chemical vapor deposition at low temperature (${\leq}200^{\circ}C$). The mixture of $SiH_4$, $NH_3$ and $H_2$ was used as source gases. The current-voltage (I-V) and the capacitance-voltage (C-V) characteristics of the films were measured. The breakdown voltage and the flat band voltage shift of samples were improved by increase of the $NH_3$ contents and $H_2$ dilution ratio. The defect states were analyzed by photoluminescence (PL) spectra. As the defect states decreased, the breakdown voltage and the flat band voltage shift increased.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.67-68
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• 2006

Floating gate non-volatile memory devices with Au nano-particles embedded in SiON or $SiO_2$ dielectrics were fabricated by digital sputtering method. The size and the density of Au are 4nm and $2{\times}10^{-12}cm^{-2}$, respectively. The floating gate memory of MOSFET with 5nm tunnel oxide and 45nm control oxide have been fabricated. This devices revealed a memory effect which due to proGrainming and erasing works perform by a gate bias stress repeatedly.