• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.389-389
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• 2010

In this paper, an investigation of the benefits of gate oxide for 8" the manufacturing of Trench MOSFETs and its impact on device performance is presented. Layout dimensions of trench power MOSFETs have been continuously reduced in order to decrease the specific on-resistance, maintaining equal vertical dimensions. We discuss experimental results for devices with a pitch size down fabricated with an unconventional gate trench topology and a simplified manufacturing scheme. The fabricated Trench MOSFETs are observed the trench gate oxidation by SEM.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.18-26
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• 2004

Back-gated silicon-on-insulator MOSFET -a threshold-voltage adjustable device-employs a constant back-gate potential to terminate source-drain electric fields and to provide carrier confinement in the channel. This suppresses shortchannel effects of nano-scale and of high drain biases, while allowing a means to threshold voltage control. We report here a theoretical analysis of this geometry to identify its natural length scales, and correlate the theoretical results with experimental device measurements. We also analyze experimental electrical characteristics for misaligned back-gate geometries to evaluate the influence on transport behavior from the device electrostatics due to the structure and position of the back-gate. The backgate structure also operates as a floating-gate nonvolatile memory (NVRAM) when the back-gate is floating. We summarize experimental and theoretical results that show the nano-scale scaling advantages of this structure over the traditional front floating-gate NVRAM.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.579-580
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• 2006

Simple nonoverlapped source/drain-to-gate MOSFETs to suppress GIDL (gate-induced drain leakage) is simulated with SILVACO simulation tool. Changing spacer thickness for adjusting length of Drain to Gate nonoverlapped region, this simulation observes on/off characteristic of nonoverlapped source/drain-to-gate MOSFETs. Off current is dramatically decreased with S/D to gate nonoverlapped length increasing. The result shows that maximum on/off current ratio is achieved by adjusting nonoverlapped length.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.1030-1033
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• 2004

We herewith report for the effect of dielectric surface modification on the electrical characteristics of organic thin-film transistors (OTFTs). The kist-jm-1 as an organic molecule for the surface modification is deposited onto the surface of zirconium oxide ($ZrO_2$) gate dielectric layer. The OTFTs are elaborated on the flexible plastic substrates through 4-level mask process to yield a simple fabrication process. In this work, we also have examined the dependence of electrical performance on the interface surface state of gate dielectric/pentacene, which may be modified by chemical properties in the gate dielectric surface.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1341-1342
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• 2006

Electrical characteristics of field-effect thin film transistors (TFTs) with p-channels of CdTe/CdHgTe core-shell nanocrystals are investigated in this paper. For the fabrication of bottom- and top-gate TFTs, CdTe/CrHgTe nanocrystals synthesized by colloidal method are first dispersed on oxidized p+ Si substrates by spin-coating, the dispersed nanoparticles are sintered at $150^{\circ}C$ to form the channels for the TFTs, and $Al_{2}O_{3}$ layers are deposited on the channels. A representative bottom-gate field-effect TFT with a bottom-gate $SiO_2$ layer exhibits a mobility of $0.21cm^2$/ Vs and an Ion/Ioff ratio of $1.5{\times}10^2$ and a representative top-gate field-effect TFT with a top-gate $Al_{2}O_{3}$ layer provides a field-effect mobility of $0.026cm^2$/ Vs and an Ion/Ioff ratio of $2.5{\times}10^2$. $Al_{2}O_{3}$ was deposited for passivation of CdTe/CdHgTe core-shell nanocrystal layer, resulting in enhanced hole mobility, Ior/Ioff ratio by 0.25, $3{\times}10^3$, respectively. The CdTe/CdHgTe nanocrystal-based TFTs with bottom- and top gate geometries are compared in this paper.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.779-782
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• 2003

The theoretical and experimental current-voltage characteristics of Erbium silicided n-type Schottky barrier tunneling transistors (SBTTs) are discussed. The theoretical drain current to drain voltage characteristics show good correspondence and the extracted Schottky barrier height is 0.24 eV. The experimentally manufactured n-type SBTTs with 60 nm gate lengths show typical transistor behaviors in drain current to drain voltage characteristics. The drain current on/off ratio is about 10$^{5}$ at low drain voltage regime in drain current to gate voltage characteristics.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.490-493
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• 2002

In this study, we have investigated optimum value for side gate length and side gate voltage of double gate (DG) MOSFET with main gate and side gate. We know that optimum side gate voltage for each side length is about 3V. Also, we know that optimum side gate length for each main gate length is about 70nm. We have presented the transconductance and subthreshold slope for each side gate length. We have simulated using ISE-TCAD tool for characteristics analysis of device.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.1027-1029
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• 2004

In this paper, we have fabricated pentacene thin film transistors (TFTs) using polyvinylphenol (PVP) copolymer and cross-linked PVP as gate insulator on glass and plastic (PET) substrate. Depending on the density of PVP and cross-link material the performance has been changed. We obtained the best device performance with the mobility of 0.32cm2/V${\cdot}$sec and the on/off current ratio of 1.19${\times}$106 for the case of 10wt% PVP copolymer mixed with 5wt% poly (melamine-co-formaldehyde). Additionally using pentacene TFTs with the above PVP gate insulator, we fabricated the integrated circuits including inverter which produced the gain of 9.7.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.647-648
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• 2006

This paper presents the design results of peripheral circuits of non-volatile memory of nano floating gate cells. The designed peripheral circuits included command decoder, decoders, sense amplifiers and oscillator, which are targeted with 0.35um technology EEPROM process for operating test and reliable test. The simulation results show each operation and test mode of output voltage for word line, bit line, well and operating of sense amplifier.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.23-30
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• 2006

This paper describes the short-channel effect(SCE), corner effect of nano-scale MuGFETs(Multiple-Gate FETs) by three-dimensional simulation. We can extract the equivalent gate number of MuGFETs(Double-gate=2, Tri-gate=3, Pi-gate=3.14, Omega-gate=3.4, GAA=4) by threshold voltage model. Using the extracted gate number(n) we can calculate the natural length for each gate devices. We established a scaling theory for MuGFETs, which gives a optimization to avoid short channel effects for the device structure(silicon thickness, gate oxide thickness). It is observed that the comer effects decrease with the reduction of doping concentration and gate oxide thickness when the radius of curvature is larger than 17 % of the channel width.