• Title/Summary/Keyword: Nano Patterning

Search Result 213, Processing Time 0.03 seconds

New Fabrication method of Planar Micro Gas Sesnor Array (집적도를 높인 평면형 가스감지소자 어레이 제작기술)

  • 정완영
    • Proceedings of the IEEK Conference
    • /
    • 2003.07b
    • /
    • pp.727-730
    • /
    • 2003
  • Thin tin oxide film with nano-size particle was prepared on silicon substrate by hydrothermal synthetic method and successive sol-gel spin coating method. The fabrication method of tin oxide film with ultrafine nano-size crystalline structure was tried to be applied to fabrication of micro gas sensor array on silicon substrate. The tin oxide film on silicon substrate was well patterned by chemical etching upto 5${\mu}{\textrm}{m}$width and showed very uniform flatness. The tin oxide film preparation method and patterning method were successfully applied to newly proposed 2-dimensional micro sensor fabrication.

  • PDF

Direct indium-tin oxide (ITO) nano-patterning using ITO nano particle solution (Indium-tin oxide (ITO) 나노 입자 용액을 이용한 직접 ITO 나노 패턴 제작 기술)

  • Yang, Gi-Yeon;Yun, Gyeong-Min;Lee, Heon
    • Proceedings of the Korean Institute of Surface Engineering Conference
    • /
    • 2009.10a
    • /
    • pp.247-247
    • /
    • 2009
  • 본 연구에서는 indium-tin oxide (ITO) 나노 입자 용액을 이용하여 간단한 공정을 통해 ITO 나노 패턴을 직접적으로 제작하는 기술에 대한 연구를 진행하였다. 이를 이용하여 300nm급 ITO 나노 dot 패턴을 제작하는데 성공하였으며 이를 glass 표면에 구현하는데 성공하였다.

  • PDF

Development of Metal nano Powder Imprinting Process for Fabrication of Conductive Tracks (금속 배선 제작을 위한 메탈 나노 파우더 임프린팅 공정기술 개발)

  • Kim, J.;Kim, H.;Lim, J.;Bae, H.;Choi, M.;Kang, S.
    • Proceedings of the Korean Society for Technology of Plasticity Conference
    • /
    • 2007.05a
    • /
    • pp.371-374
    • /
    • 2007
  • A method for metal nano powder imprinting is proposed as a patterning process for conductive tracks that is inexpensive and scalable down to the nanoscale. Conductive tracks with line widths of $0.5{\sim}20{\mu}m$ were fabricated using this method. The processing conditions were optimized to avoid various types of defects, and to increase the degree of sintering and electric conductivity of the imprinted conductive tracks. The mean electric resistivity of the conductive tracks imprinted under optimum conditions was $8.95{\mu}{\Omega}{\cdot}cm$, which is in the range required for practical applications.

  • PDF

Silicon Nano Patterning Using Focused ion Beam: Simulation and Fabrication (집속이온빔을 이용한 실리콘 나노 패터닝: 시뮬레이션과 가공)

  • Han J.;Min B.K.;Lee S.J.
    • Proceedings of the Korean Society of Precision Engineering Conference
    • /
    • 2006.05a
    • /
    • pp.489-490
    • /
    • 2006
  • To establish fabrication techniques for nano structure understanding of focused ion beam (FIB) milling process is required. In this study the mathematical model containing the factors related to FIB milling is developed to acquire the optimal fabrication condition. Then, the model is verified by comparison with various nano pattern fabricated in actual FIB system. Consequently, it is demonstrated that the nano patterns with the smallest pitch can be fabricated using developed FIB milling model.

  • PDF

Scanning Kelvin Probe Microscope analysis of Nano-scale Patterning formed by Atomic Force Microscopy in Silicon Carbide (원자힘현미경을 이용한 탄화규소 미세 패터닝의 Scanning Kelvin Probe Microscopy 분석)

  • Jo, Yeong-Deuk;Bahng, Wook;Kim, Sang-Cheol;Kim, Nam-Kyun;Koo, Sang-Mo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2009.11a
    • /
    • pp.32-32
    • /
    • 2009
  • Silicon carbide (SiC) is a wide-bandgap semiconductor that has materials properties necessary for the high-power, high-frequency, high-temperature, and radiation-hard condition applications, where silicon devices cannot perform. SiC is also the only compound semiconductor material. on which a silicon oxide layer can be thermally grown, and therefore may fabrication processes used in Si-based technology can be adapted to SiC. So far, atomic force microscopy (AFM) has been extensively used to study the surface charges, dielectric constants and electrical potential distribution as well as topography in silicon-based device structures, whereas it has rarely been applied to SiC-based structures. In this work, we investigated that the local oxide growth on SiC under various conditions and demonstrated that an increased (up to ~100 nN) tip loading force (LF) on highly-doped SiC can lead a direct oxide growth (up to few tens of nm) on 4H-SiC. In addition, the surface potential and topography distributions of nano-scale patterned structures on SiC were measured at a nanometer-scale resolution using a scanning kelvin probe force microscopy (SKPM) with a non-contact mode AFM. The measured results were calibrated using a Pt-coated tip. It is assumed that the atomically resolved surface potential difference does not originate from the intrinsic work function of the materials but reflects the local electron density on the surface. It was found that the work function of the nano-scale patterned on SiC was higher than that of original SiC surface. The results confirm the concept of the work function and the barrier heights of oxide structures/SiC structures.

  • PDF