• Korean Chemical Engineering Research
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• v.46 no.3
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• pp.498-505
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• 2008

The selective catalytic oxidation of ammonia was carried out in the presence of natural manganese ore (NMO) and manganese as catalysts using a homemade 1/4" reactor at $10,000hr^{-1}$ of space velocity. The inlet ammonia concentration was maintained at 2,000 ppm, with an air balance. The manganese catalyst resulted in a substantial ammonia conversion, with adsorption activation energies of oxygen and ammonia of 10.5 and 22.7 kcal/mol, respectively. Both $T_{50}$ and $T_{90}$, defined as the temperatures where 50% and 90% of ammonia, respectively, are converted, decreased significantly when alumina-supported manganese catalyst was applied. Increasing the manganese weight percent by 15 wt% increased the lower temperature activity, but 20 wt% of manganese had an adverse effect on the reaction results. An important finding of the study was that the manganese catalyst benefits from a strong sulfur tolerance in the conversion of ammonia to nitrogen.

• Geophysics and Geophysical Exploration
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• v.6 no.2
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• pp.71-76
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• 2003

Accurate estimation of the first arrival travel time is an essential task to obtain a high resolution velocity tomogram. Accuracy of the travel time estimation may be influenced by two factors; geological and mechanical. A serious mechanical factor is the source firing control problems. We found the control problems in the records generated by tome impulsive borehole sources. The problems are; irregular firing control and uncertainty in estimation of the absolute firing-times shown in records. Definitely, the time difference will introduce an error to the first arrival times, and accordingly; it will cause some distortion in the resulting velocity tomogram. A method to determine the firing time is suggested here. The method determines the optimum onset time by comparing the horizontal and the NMO velocity with various amount of delay time adjustment.

• Korean Journal of Materials Research
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• v.1 no.3
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• pp.132-138
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• 1991

A comparision was made on the influence of BPSG flow temperatures on the electrical properties in submicron CMOS DRAMs containing two BPSG layers. Three different combinations of BPSG flow temperature such as $850^{\circ}C/850^{\circ}C,\;850^{\circ}C/900^{\circ}C,\;and\;900^{\circ}C/900^{\circ}C$ were employed and analyzed in terms of threshold, breakdown and isolation voltage along with sheet resistance and contact resistance. In case of $900^{\circ}C/900^{\circ}C$ flow, the threshold voltage of NMOS was decreased rapidly in channel length less than $0.8\mu\textrm{m}$ with no noticeable change in PMOS and a drastic decrease in breakdown voltages of NMOS and PMOS was observed in channel length less than and equal to $0.7\mu\textrm{m}$ and $0.8\mu\textrm{m}$, respectively. Little changes in threshold and breakdown voltages of NMOS and PMOS, however, were shown down to channel length of $0.6\mu\textrm{m}$ in case of $850^{\circ}C/850^{\circ}C$ flow. The isolation voltage was increased with decreasing BPSG flow temperature. A significant increase in the sheet resistance and contact resistance was noticeable with decreasing BPSG flow temperature from $900^{\circ}C$ to $850^{\circ}C$. All these observations were rationalized in terms of dopant diffusion and activation upon BPSG flow temperature. Some suggestions for improving contact resistance were made.

• 발명특허
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• v.10 no.8 s.114
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• pp.64-64
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• 1985

금성반도체(대표 : 구자두)는 미국, 일본에 이어 세계 3번째로 첨단반도체제품인 CMOS 64K SRAM을 자체개발하는데 성공했다. 국내 최초로 개발된 금성반도체의 CMOS 64K SRAM은 우리나라의 반도체 기술수준을 선진국 수준으로 성큼 다가서게 했다. CMOS 64K SRAM은 NMOS의 256K DRAM에 비해 작동속도가 2배이상 빠를 뿐만 아니라 재충전이 필요없는 완전한 스태틱(static) RAM으로 대용량$\cdot$고속$\cdot$고신뢰성을 요하는 고성능 컴퓨터, 통신장비등 첨단 산업용 기기의 기억장치에 주로 사용된다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.1
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• pp.157-163
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• 1998

A neural network structure able to perform the operations of analogue and binary addition is proposed. The network employs Hopfield' model of a neuron with the connection elements specified on the basis of an analysis of the energy function. Simulation using NMOS neurons has shown convergence predominantly to the correct global minima.

• Applied Chemistry for Engineering
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• v.9 no.2
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• pp.278-285
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• 1998

In a fixed bed reactor, adsorption capacity of $SO_2$ in simulated flue gases was investigated with NMO(natural manganese ore), composed of various metal oxides, iron ore and $CuO/{\gamma}-Al_2O_3$ as adsorbents. The experiment carried out in a fluidized bed reactor with variables such as gas velocity, temperature and particle size. Iron ore was excluded in the fluidized bed reactor experiment for the lower adsorption capacity. The adsorption of $SO_2$ in metal oxide is a typical chemisorption because the adsorption capacity of all adsorbents increased with temperature. The effect of particle size on the adsorption capacity was varied with the ratio, $U_o/U_{mf}$ and the difference of $U_o-U_{mf}$. $U_o$ is the gas velocity, $U_{mf}$ is the minimum fluidization gas velocity. $U_o/U_{mf}$ and $U_o-U_{mf}$ explain the behavior of the gas and solids in the fluidized bed reactor. From the performance equation of the fluidized bed reactor, kinetic reaction rate constants were obtained by the non-linear least square method. The adsorption capacity of NMO proved the potential use of $SO_2$ adsorbents.

• Journal of Advanced Navigation Technology
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• v.7 no.2
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• pp.211-216
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• 2003

In this paper, characteristics of Ta-Ti alloy was studied as a gate electrode for NMOS devices to replace the widely used polysilicon. Ta-Ti alloy was deposited directly on $SiO_2$ by a co-sputtering method using two of Ta and Ti targets. The sputtering power of each metal target was 100W. To compare with Ta-Ti, Ta deposited with a 100W sputtering power was fabricated as well. In order to investigate the thermal/chemical stability of the Ta-Ti alloy gate, the alloy was annealed at $600^{\circ}C$ with rapid thermal annealer. No appreciable degradation of the device was observed. Also the results of electrical analysis showed that the work function of Ta-Ti metal alloy was about 4.1eV which was suitable for NMOS devices and sheet resistance of alloy was lower than that of polysilicon.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.7 s.337
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• pp.5-12
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• 2005

The device performance of nano-scale center-channel (CC) double-gate (DG) MOSFET structure was investigated by numerically solving coupled Schr$\"{o}$dinger-Poisson and current continuity equations in a self-consistent manner. The CC operation and corresponding enhancement of current drive and transconductance of CC-NMOS are confirmed by comparing with the results of DG-NMOS which are performed under the condition of 10-80 nm gate length. Device optimization was theoretically performed in order to minimize the short-channel effects in terms of subthreshold swing, threshold voltage roll-off, and drain-induced barrier lowering. The simulation results indicate that DG-MOSFET structure including CC-NMOS is a promising candidates and quantum-mechanical modeling and simulation calculating the coupled Schr$\"{o}$dinger-Poisson and current continuity equations self-consistently are necessary for the application to sub-40 nm MOSFET technology.

• The Journal of Engineering Geology
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• v.16 no.2 s.48
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• pp.161-169
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• 2006

A short seismic reflection survey was performed to map the basement and the upper units in the Gomso Bay. This research was mainly aimed at clarifying the basement by improving the signal-to-noise ratio in data processing steps. The strategies employed in this research included enhancement of the signal interfered with large-amplitude noise, through pre- and post-stack processing such as time-variant filtering, bad trace edit, careful muting after f-k filter and NMO correction. The subsurface structure mapped from this survey mainly consists of the top of basement and the upper three units, which were well correlated to the result from the previously conducted MT survey. Furthermore seismic section clarifies approximately 30m deep subhorizontal event of the top of the basement, which was not shown in the central portion of the MT section due to data qualify.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.191-191
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• 2007

유효 산화막 두께가 약 2.0nm 정도의 $ZrO_2$ 절연막 위에 Ta-Mo 금속 합금과 Ru-Zr 금속 합금을 Co-sputtering 방법을 이용하여 여러 가지 일함수를 갖는 MOS capacitor를 제작하여 전기적 재료적 특성에 관하여 연구를 하였다. 그 결과 각각의 금속 합금 게이트는 4.1eV 에서 5.1eV 사이의 다양한 일함수를 나타냈으며, $400^{\circ}C$, $500^{\circ}C$, $600^{\circ}C$, $700^{\circ}C$, $800^{\circ}C$ RTA 후의 C-V특성 곡선 및 I-V 측정을 통하여 누설전류를 확인하였다. 그 결과 Ta-Mo 금속 합금의 경우 스퍼터링 파워가 100W/70W에서 NMOS에 적합한 일함수를 가졌으며, Ru-Zr 금속 합금의 경우 스퍼터링 파워가 50W/100W에서 NMOS에 적합한 일함수를 가졌다. 열처리 후의 C-V특성 곡선에서도 정전용랑 값이 거의 변하지 않았으며 평탄 전압의 변화도 거의 없었다. 누설전류 특성에서는 물리적 두께가 비슷한 기존의 $SiO_2$ 절연막에서 실험결과와 비교하여 약 100배 정도 감소되었음을 알 수 있었다. 또한 기존의 실험들에서 나타난 열처리 후의 $ZrO_2$ 절연막과 Si 기판 사이의 Interfacial layer 의 동반 두께 증가로 인한 전기적 특성 저하가 나타나지 않는 줄은 특성을 보여준다.