• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.87-97
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• 2013

Negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) are critical circuit reliability issues in highly scaled CMOS technologies. In this paper, we analyze the impacts of NBTI and PBTI on SRAM $V_{MIN}$, and present a design solution for mitigating the impact of NBTI and PBTI on SRAM $V_{MIN}$. Two different types of SRAM $V_{MIN}$ (SNM-limited $V_{MIN}$ and time-limited $V_{MIN}$) are explained. Simulation results show that SNM-limited $V_{MIN}$ is more sensitive to NBTI while time-limited $V_{MIN}$ is more prone to suffer from PBTI effect. The proposed NBTI/PBTI-aware control of wordline pulse width and woldline voltage improves cell stability, and mitigates the $V_{MIN}$ degradation induced by NBTI/PBTI.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.122-122
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• 2008

Recently, Metal/Alumina/Silicon-Nitride/Silicon-Oxide/Silicon (MANOS) structures are one of the most attractive candidates to realize vertical scaling of high-density NAND flash memory [1]. However, as ANO layers are miniaturized, negative and positive bias temperature instability (NBTI/PBTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density increase, ${\Delta}D_{it}$, the gate leakage current, ${\Delta}I_G$. and the retention characteristics, in MONOS capacitors, becomes an important issue in terms of reliability. It is well known that tunnel oxide degradation is a result of the oxide and interfacial traps generation during FN (Fowler-Nordheim) stress [2]. Because the bias temperature stress causes an increase of both interfacial-traps and fixed oxide charge could be a factor, witch can degrade device reliability during the program and erase operation. However, few studies on NBTI/PBTI have been conducted on improving the reliability of MONOS devices. In this work, we investigate the effect of post-annealing gas on bias temperature instability (BTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density shift, ${\Delta}I_G$ retention characteristics, and the gate leakage current characteristics of MANOS capacitors. MANOS samples annealed at $950^{\circ}C$ for 30 s by a rapid thermal process were treated via additional annealing in a furnace, using annealing gases $N_2$ and $N_2-H_2$ (2 % hydrogen and 98 % nitrogen mixture gases) at $450^{\circ}C$ for 30 min. MANOS samples annealed in $N_2-H_2$ ambient had the lowest flat band voltage shift, ${\Delta}V_{FB}$ = 1.09/0.63 V at the program/erase state, and the good retention characteristics, 123/84 mV/decade at the program/erase state more than the sample annealed at $N_2$ ambient.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.6
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• pp.25-30
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• 2013

In nanoscale MOSFET technology, aging effects such as Negative Bias Temperature Instability(NBTI), Hot carrier Injection(HCI), Time Dependent Dielectric Breakdown (TDDB) and so on which affect circuit reliability can lead to severe degradation of digital circuit performance. Therefore, this paper has proposed the adaptive compensation circuit to overcome the aging effects of digital circuits. The proposed circuit deploys a power gating structure with variable power switch width and variable forward body-biasing voltage in order to adaptively compensate for aging induced performance degradation, and has been designed in 45nm technology.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.08a
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• pp.147-147
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• 2009

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.1-8
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• 2006

In this paper, reliability (HCI, NBTI) and device performance of nano-scale CMOSFETs with different channel stress were investigated. It was shown that NMOS and PMOS performances were improved by tensile and compressive stress, respectively, as well known. It is shown that improved device performance is attributed to the increased mobility of electrons or holes in the channel region. However, reliability characteristics showed different dependence on the channel stress. Both of NMOS and PMOS showed improved hot carrier lifetime for compressive channel stress. NBTI of PMOS also showed improvement for compressive stress. It is shown that $N_{it}$ generation at the interface of $Si/SiO_2$ has a great effect on the reliability. It is also shown that generation of positive fixed charge has an effect in the NBTI. Therefore, reliability as well as device performance should be considered in developing strained-silicon MOSFET.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.4
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• pp.33-39
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• 2014

In this paper, a new on-chip aging sensing circuit based on flip-flops is proposed to detect a circuit failure of MOSFET digital circuits casued by aging phenomenon such as HCI and BTI. The proposed circuit uses timing windows to warn against a guardband violation of sequential circuits, and generates three warning bits right before circuit failures occur. The generated bits can apply to an adaptive self-tuning method for reliable system design as control signals. The aging sensor circuit has been implemented using 0.11um CMOS technology and evaluated by $4{\times}4$ multiplier with power gating structure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.18-23
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• 2009

The effect of hydrogen-nitrogen annealing on the interface trap properties of Metal-Oxide-Nitride-Oxide-Silicon (MONOS) capacitors is investigated by analyzing the capacitors' gate leakage current and the interface trap density between the Si and $SiO_2$ layer. MONOS samples annealed at $850^{\circ}C$ for 30 s by rapid thermal annealing (RTA) are treated by additional annealing in a furnace, using annealing eases $N_2$ and 2% hydrogen and 98% nitrogen gas mixture $(N_2-H_2)$ at $450^{\circ}C$ for 30 mins. Among the three samples as-deposited, annealed in $N_2$ and $N_2-H_2$, MONOS sample annealed in an $N_2-H_2$ environment is found to have the lowest increase of interface-trap density from the capacitance-voltage experiments. The leakage current of sample annealed in $N_2-H_2$ is also lower than that of sample annealed in $N_2$.