• Journal of KIISE:Computer Systems and Theory
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• v.27 no.2
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• pp.149-159
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• 2000

In this paper, we propose a new class of MIN (Multistage Interconnection Network) called SCMIN(ShortCut MIN) which can form a cheap and efficient packet switching interconnection network. SCMIN satisfies full access capability(FAC) and has multiple redundant paths between processor-memory pairs even though SCMIN is constructed with 2.5N-4 SEs which is far fewer SEs than that of MINs. SCMIN can be constructed suitable for localized communication by providing the shortcut path and multiple paths inside the processor-memory cluster which has frequent data communications. Therefore, SCMIN can be used as an attractive interconnection network for parallel applications with a localized communication pattern in shared-memory multiprocessor systems.

• ETRI Journal
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• v.16 no.3
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• pp.27-41
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• 1994

This paper provides a performance study of multistage interconnection networks in packet switching environment. In comparison to earlier work, the model is more extensive - it includes several parameters such as multiple-packet messages, variable buffer size, and wait delay at a source. The model is also uniformly applied to several representative networks and thus provides a basis for fair comparison as well as selection of optimal values for parameters. The complexity of the model required use of simulation. However, a partial analytical model is provided to measure the congestion in a network.

• Proceedings of the IEEK Conference
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• 2001.06c
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• pp.199-202
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• 2001

In this paper, we proposed and analyzed a new class of irregular fault-tolerant multistage interconnection network named as Extended-QT(Quad Tree) network. E-QT network is extended QT network. A unique path MIN usually is low hardware complexity and control algorithm. So we proposes a class of multipath MIN which are obtained by adding self-loop auxiliary links at the a1l stages in QT(Quad Tree) networks so that they can provide more paths between each source-destination pair. The routing of proposed structure is adaptived and is based by a routing tag. Starting with the routing tag for the minimum path between a given source-destination pair, routing algorithm uses a set of rules to select switches and modify routing tag. Trying the self-loop auxiliary link when both of the output links are unavailable. If the trying is failure, the packet discard. In simulation, an index of performance called reliability and cost are introduced to compare different kinds of MINs. As a result, the prouosed MINs have better capacity than 07 networks.

• Journal of KIISE:Information Networking
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• v.34 no.3
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• pp.193-202
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• 2007

In this paper, a performance evaluation model of the Multistage Interconnection Network(MIN) with the multiple-buffered crossbar switches under Hot-spot environment is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the MIN. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch. The performance of the multiple-buffered $a{\times}a$ crossbar switch is analyzed. Steady state probability concept is used to simplify the analyzing processes. Two important parameters of the network performance, throughput and delay, are then evaluated. To validate the proposed analysis model, the simulation is carried out on a Baseline network that uses the multiple buffered crossbar switches. Less than 2% differences between analysis and simulation results are observed. It is also shown that the network performance is significantly improved when the small number of buffer spaces is given. However, the throughput elevation is getting reduced and network delay becomes increasing as more buffer spaces are added in a switch.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.37 no.9
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• pp.663-670
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• 1988

Advances in VLSI technology have made it possible to have a larger number of processing elements to be included in highly parallel processor system. A system with a large number of processing elements and memory requires a complex data path. Multistage Interconnection networks(MINS) are useful in providing programmable data path between processing elements and memory modules in multiprocessor system. In this thesis, the performance of MINS for the star network has been analyzed and compared with other networks, such as generalized shuffle network, delta network, and referenced crossbar network.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.14 no.6
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• pp.15-23
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• 1996

• Proceedings of the Korean Information Science Society Conference
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• 2005.11a
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• pp.166-168
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• 2005

본 논문에서는, axa 출력 버퍼 스위치로 구성된 핫스팟이 발생된 상황 하에서 다단 연결 망(Multistage interconnection Network, MIN)의 성능 예측 모형을 제안하였다. 제안한 성능 예측 오형은 먼저 네트워크 내부 임의 스위치 입력 단에 유입되는 데이터 패킷이 스위치 내부에서 전송되는 유형을 확률적으로 분석하여 설계하였다. 성능분석 모형은 스위치에 장착된 버퍼의 개수와 무관하게 버퍼를 장착한 axa 스위치의 성능, 네트워크 정상상태 처리율(Normalized Throughput, NT)과 네트워크 지연시간(Network Delay)의 예측이 가능하고, 나아가서 이들로 구성진 모든 종류의 다단 연결망 성능 분석에 적용이 용이하다. 제안한 수학적 성능 분석 연구의 실효성 검증을 위하여 병행된 시뮬레이션 결과는 상호 미세한 오차 범위 내에서 모형의 예측 데이터와 일치하는 결과를 보여 분석 모형의 타당성을 입증하였다.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2004.10a
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• pp.640-643
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• 2004

As the size of a network increases, the network complexity and maintenance cost is high. In literatures, many cost factors of multistage interconnection networks were intensively investigated. However, in some parts, these types of cost definition are not satisfactory enough since they don't relate the cost measure to technology closely and also fail to incorporate exact tradeoffs in designing the network. In this paper, we propose some cost effective measures which combine the cost factors with performance-related reliability measures, and compare several networks for a guidance to select a certain case depending on the principal concerns for use.

• ETRI Journal
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• v.45 no.1
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• pp.60-74
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• 2023

Integration of the machine learning (ML) technique in all-optical networks can enhance the effectiveness of resource utilization, quality of service assurances, and scalability in optical networks. All-optical multistage interconnection networks (MINs) are implicitly designed to withstand the increasing highvolume traffic demands at data centers. However, the contention resolution mechanism in MINs becomes a bottleneck in handling such data traffic. In this paper, a select list of ML algorithms replaces the traditional electronic signal processing methods used to resolve contention in MIN. The suitability of these algorithms in improving the performance of the entire network is assessed in terms of injection rate, average latency, and latency distribution. Our findings showed that the ML module is recommended for improving the performance of the network. The improved performance and traffic grooming capabilities of the module are also validated by using a hardware testbed.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10c
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• pp.244-246
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• 1999

본 논문에서는, multiple-buffered crossbar 스위치를 이용한 다층 연결 망의 성능 분석 모형을 제안하고, 스위치에 장착된 buffer의 개수 증가에 따른 성능 향상 추이를 분석하였다. Buffered 스위치 기법은 다층 연결 망 (Multistage Interconnection Network, MIN)의 내부의 데이터 충돌 문제를 효과적으로 해결할 수 있는 방법으로 알려져 있다. 제안된 성능 분석 모형은 먼저 네트웍 내부 임의 스위치 입력 단에 유입되는 데이터 패킷이 buffered 스위치 내부에서 전송되는 패턴을 확률적으로 분석하여 수립하였다. 분석 모형의 수학적 복잡도 절감을 위하여 확률식 유도 과정에 정상상태 확률 rosa(steady state probability)을 도입하였다. 제안한 모형은 스위치의 크기 및 스위치에 장착된 buffer의 수와 무관하게 확대 적용이 가능하다. 제안한 수학적 성능 분석 연구의 실효성 검증을 위하여 병행된 시뮬레이션 처리 결과는 상호 미세한 오차 범위 내에서 모형의 예측 데이터와 일치하는 결과를 보여 분석 모형의 타당성을 입증하였다. 2$\times$2 스위치로 구성된 8$\times$8 MIN을 대상으로 분석을 시행한 결과 스위치에 2~4개의 buffer를 장착했을 경우 unbuffer 스위치 경우와 비교하여 네트웍 정상상태 Throughout의 증가율이 높고 네트웍 Delay 또한 낮아져 효율적인 것으로 나타났다. 따라서 2~2 crossbar 스위치로 구성된 MIN의 경우 스위치에 장착된 buffer의 개수가 네 개 정도일 경우가 가격 대 성능비 면에서 가장 유리한 것으로 연구되었다.