• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.2
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• pp.19-26
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• 2015

This paper presents design, fabrication, and performance evaluation of a high voltage power supply for Carbon Nano Tube-based planar light sources. The proposed power supply employs an LLC resonant half-bridge converter and a sixfold voltage-multiplying rectifier. Steady-state characteristics of the voltage-multiplying rectifier are analyzed and used to derive the input-to-output voltage conversion ratio of the power supply. The input-to-output frequency response characteristics of the LLC tank circuit are analyzed and utilized in designing a proto-type power supply which produces a 15 KV output using a 400 V input source. The high-voltage transformer is fabricated using a sectional bobbin structure with an epoxy impregnation, in order to provide sufficient insulation for high voltage operations. The performance of the proposed power supply is confirmed with stable and reliable operations at the 15 KV output from no load to nominal load conditions. The proposed power supply is well suited as an electric ballast required stable operations of Carbon Nano Tube-based planar light sources.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.4
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• pp.3-11
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• 2000

In this paper, we design modular multiplication systolic array and exponentiation processor having n bits message black. This processor uses Montgomery algorithm and LR binary square and multiply algorithm. This processor consists of 3 divisions, which are control unit that controls computation sequence, 5 shift registers that save input and output values, and modular exponentiation unit. To verify the designed exponetion processor, we model and simulate it using VHDL and MAX+PLUS II. Consider a message block length of n=512, the time needed for encrypting or decrypting such a block is 59.5ms. This modular exponentiation unit is used to RSA cryptosystem.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.2
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• pp.123-131
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• 2002

In this paper, a new standard basis parallel ternary-valued multiplier circuit designed using current mode CMOS is presented. Prior to constructing the GF(3$^{ｍ}$) multiplier circuit, we provide a GF(3) adder and a GF(3) multiplier with truth tables and symbolize them, and also design them using current mode CMOS circuit. Using the basic ternary operation concept, a ternary adder and a multiplier, we develop the equations to multiply arbitrary two elements over GF(3$^{ｍ}$). Following these equations, we can design a multiplier generalized to GF(3$^{ｍ}$). For the proposed circuit in this paper, we show the example in GF(3$^{3}$). In this paper, we assemble the operation blocks into a complete GF(3$^{ｍ}$) multiplier. Therefore the proposed circuit is easy to generalize for m and advantageous for VLSI. Also, it need no memory element and the latency not less fewer than other circuit. We verify the proposed circuit by functional simulation and show its result.

• Journal of Korean Society for Quality Management
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• v.49 no.1
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• pp.17-29
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• 2021

Purpose: During 2015-2019, the average amount of political donation to the national assembly members in Korea was 1,000 won per person. Despite its benefits such as receiving tax credits, the donation system has not been actively practiced. This paper aims to promote political donations by suggesting a recommendation system of national assembly members by analysing the bills they proposed. Methods: In this paper, we propose a recommendation system based on two aspects: how similar the newly proposed or ammended bills are to the sponsors' interest (similarity index) and how much effort national assembly members put into those bills (intensity index). More than 25,000 bills were used to measure the recommendation quality index consisted with both the similarity and the intensity indices. Word2vec was used to calculate the similarity index of the bills proposed by the national assembly member to the sponsor's interest. The intensity index is calculated by diving the number of newly proposed or entirely revised bills with the number of senators who took part in those bills. Subsequently, we multiply the similarity index by the intensity index to obtain the recommendation quality index that can assist sponsors to identify potential assembly members for their donation. Results: We apply the proposed recommendation system to personas for illustration. The recommendation system showed an average f1 score about 0.69. The analysis results provide insights in recommendation for donation. Conclusion: n this study, the recommendation system was proposed to promote a political donation for national assembly members by creating the recommendation quality index based on the similarity and the intensity indices. We expect that the system presented in this paper will lower user barriers to political information, thereby boosting political sponsorship and increasing political participation.

• Journal of the Korean Society for Precision Engineering
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• v.23 no.6 s.183
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• pp.96-103
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• 2006

To establish of standard technique of nano-length measurement in 2D plane, new AFM system has been designed. In the long range (about several tens of ${\mu}m$), measurement uncertainty is dominantly affected by the Abbe error of XY scanning stage. No linear stage is perfectly straight; in other words, every scanning stage is subject to tilting, pitch and yaw motion. In this paper, an AFM system with minimum offset of XY sensing is designed. And XY scanning stage is designed to minimize rotation angle because Abbe errors occur through the multiply of offset and rotation angle. To minimize the rotation angle optimal design has performed by maximizing the stiffness ratio of motion direction to the parasitic motion direction of each stage. This paper describes the design scheme of full AFM system, especially about XY stage. Full range of fabricated XY scanner is $100{\mu}m\times100{\mu}m$. And tilting, pitch and yaw motion are measured by autocollimator to evaluate the performance of XY stage. As a result, XY scanner can have good performance. Using this AFM system, 3um pitch specimen was measured. The uncertainty of total system has been evaluated. X and Y direction performance is different. X-direction measuring performance is better. So to evaluate only ID pitch length, X-direction scanning is preferable. Its expanded uncertainty(k=2) is $\sqrt{(3.96)^2+(4.10\times10^{-5}{\times}p)^2}$ measured length in nm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.3
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• pp.517-526
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• 2000

In this paper, we propose the trellis coded spread spectrum communication system with one channel signal selection of the subset by the PN code. This paper proposes the Viterbi decoder that have the squared Euclidean distance of the order phase difference as well as 1st order phase difference as the branch metrics by using the multiple symbol detection method. TCM method was developed to overcome limited power and bandwidth efficiently in digital communication. we multiply one of convolution code's output data to PN code for applying TCM to the spread spectrum. We investigated the performance of the direct sequence/spread spectrum communication system with trellis coded modulation. In this system, we could improved the coding gain in the spread spectrum.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.778-781
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• 2007

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyze the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture protype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the target RSA processor.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.11 s.102
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• pp.1123-1130
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• 2005

In this paper, we propose an improved side information processing scheme which is important in the sub-block phase weighting(SPW) method for the peak-to-average power ratio(PAPR) reduction. SPW method is to divide the input OFDM subchannels into several subblocks and to multiply phase weighting with each subblocks, properly for the reduction of the peak power. SPW method is similar to the conventional PTS method when the number of sub-carriers, signal modulation format and the number of subblocks are the same. However, unlike the conventional PTS(Partial Transmit Sequence) and SLM(Selected Mapping) method using many stages of IFFT(Inverse Fast Fourier Transform), SPW method only needs one IFFT. Although PAPR can be reduced by SPW method, complex computation burden still remains. In this paper the flipping algorithm and the full iteration algorithm are used f3r the phase control method. Through the computer simulation, we analyze and discuss the properties and the performance of the suggested method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6C
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• pp.637-644
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• 2006

This paper presents performance and implementation comparisons of standard and fast DCT algorithms that are commonly used for subband filter bank in MPEG audio coders. The comparison is made according to the architectural difference of the implementation hardware. Fast DCT algorithms are known to have much less computational complexity than the standard method that involves computing a vector dot product of cosine coefficient. But, due to structural irregularity, fast DCT algorithms require extra cycles to generate the addresses for operands and to realign interim data. When algorithms are implemented using DSP processors that provide special operations such as single-cycle MAC (multiply-accumulate), zero-overhead nested loop, the standard algorithm is more advantageous than the fast algorithms. Also, in case of the finite-precision processing, the error performance of the standard method is far superior to that of the fast algorithms. In this paper, truncation errors and algorithmic suitability are analyzed and implementation results are provided to support the analysis.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.1
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• pp.65-70
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• 2008

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b${\times}$32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyze the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture prototype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the target RSA processor.