• Journal of the Institute of Convergence Signal Processing
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• v.2 no.3
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• pp.102-109
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• 2001

In this paper, a new multiplication algorithm which describes the methods of constructing a multiplierover GF(p$^{m}$ ) was presented. For the multiplication of two elements in the finite field, the multiplication formula was derived. Multiplier structures which can be constructed by this formula were considered as well. For example, both GF(3) multiplication module and GF(3) addition module were realized by current-mode CMOS technology. By using these operation modules the basic cell used in GF(3$^{m}$ ) multiplier was realized and verified by SPICE simulation tool. Proposed multipliers consisted of regular interconnection of simple cells use regular cellular arrays. So they are simply expansible for the multiplication of two elements in the finite field increasing the degree m.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.8
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• pp.416-422
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• 2006

With the increasing demand for renewable energy, distributed power included in fuel cells have been studied and developed as a future energy source. For this system, a power conversion circuit is necessary to interface the generated power to the utility. In many cases, a high step-up dc/dc converter is needed to boost low input voltage to high voltage output. Conventional methods using cascade dc/dc converters cause extra complexity and higher cost. The conventional topologies to get high output voltage use flyback dc/dc converters. They have the leakage components that cause stress and loss of energy that results in low efficiency. This paper presents a high boost converter with a voltage multiplier and a coupled inductor. The secondary voltage of the coupled inductor is rectified using a voltage multiplier and series-connected with the boost voltage of primary voltage of the coupled inductor. Therefore, high boost voltage is obtained with low duty cycle. Theoretical analysis and experimental results verify the proposed solutions using a 300W prototype.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.617-620
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• 2001

This paper describes an efficient error-compensation technique for designing a low-error truncated Booth multiplier that receives two N-bit numbers and produces an N-bit product by eliminating the N least-significant bits. Applying the proposed method, a truncated Booth multiplier for area-efficient and low-power applications has been designed, and its performance (truncation error, area) was analyzed. Since the truncated Booth multiplier omits about half the partial product generators and adders, it has an area reduction by about 35%~40%, compared with non-truncated parallel multipliers. Error analysis shows that the proposed approach reduces the average truncation error by approximately 30%~40%, compared with conventional methods.

• Communications for Statistical Applications and Methods
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• v.2 no.2
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• pp.101-114
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• 1995

In this paper we consider the multiple unit root tests both for the regular and seasonal unit roots based on the Lagrange Multiplier(LM) principle. Unlike Li(1991)'s method, by plugging the restricted maximum likelihood estimates of the nuisance parameters in the model, we propose a Lagrange multiplier test which does not depend on the existence of the nuisance parameters. The asymptotic distribution of the proposed statistic is derived and empirical percentiles of the test statistic for selected seasonal periods are provided. The power and size of the test statistic for examined for finite samples through a Monte Carlo simularion.

• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.3
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• pp.389-395
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• 2011

Since Elliptic Curve Cryptosystems(ECCs) support the same security as RSA cryptosystem and ElGamal cryptosystem with 1/6 size key, ECCs are the most efficient to smart cards, cellular phone and small-size computers restricted by high memory capacity and power of process. In this paper, we explicitly explain methods for finite fields operations used in ECC, and then construct some composite fields over finite fields which are secure under Weil's decent attack and maximize the speed of operations. Lastly, we propose a fast multiplier over our composite fields.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.1-9
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• 2007

For an efficient implementation of cryptosystems based on arithmetic in a finite field $GF(2^n)$, their hardware implementation is an important research topic. To construct a multiplier with low area complexity, the divide-and-conquer technique such as the original Karatsuba-Ofman method and multi-segment Karatsuba methods is a useful method. Leone proposed an efficient parallel multiplier with low area complexity, and Ernst at al. proposed a multiplier of a multi-segment Karatsuba method. In [1], the authors proposed new $MSK_5$ and $MSK_7$ methods with low area complexity to improve Ernst's method. In [3], the authors proposed a method which combines $MSK_2$ and $MSK_3$. In this paper we propose an efficient multiplication method by combining $MSK_2,\;MSK_3\;and\;MSK_5$ together. The proposed method reduces $116{\cdot}3^l$ gates and $2T_X$ time delay compared with Gather's method at the degree $25{\cdot}2^l-2^l with l>0.

• Journal of IKEEE
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• v.26 no.4
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• pp.736-741
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• 2022

Lattice-based cryptography is the most practical post-quantum cryptography because it enjoys strong worst-case security, relatively efficient implementation, and simplicity. Ring learning with errors (R-LWE) is a public key encryption (PKE) method of lattice-based encryption (LBC), and the most important operation of R-LWE is the modular polynomial multiplication of rings. This paper proposes a method for optimizing modular multipliers based on approximate computing (AC) technology, targeting the medium-security parameter set of the R-LWE cryptosystem. First, as a simple way to implement complex logic, LUT is used to omit some of the approximate multiplication operations, and the 2's complement method is used to calculate the number of bits whose value is 1 when converting the value of the input data to binary. We propose a total of two methods to reduce the number of required adders by minimizing them. The proposed LUT-based modular multiplier reduced both speed and area by 9% compared to the existing R-LWE modular multiplier, and the modular multiplier using the 2's complement method reduced the area by 40% and improved the speed by 2%. appear. Finally, the area of the optimized modular multiplier with both of these methods applied was reduced by up to 43% compared to the previous one, and the speed was reduced by up to 10%.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.636-639
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• 2004

In present, there are many methods such as DCT, Wavelet Transform, or Quantization -to the image compression field, but the basic image compression method have based on DCT. The representative thing of the efficient techniques for information compression is DCT method. It is more superior than other information conversion method. It is widely applied in digital signal processing field and MPEG and JPEG which are selected as basis algorithm for an image compression by the international standardization group. It is general that DCT is consisted of using multiplier with main arithmetic blocks having many arithmetic amounts. But, the use of multiplier requires many areas when hardware is embodied, and there is fault that the processing speed is low. In this paper, we designed the hardware module that could run high-speed operation using row-column separation calculation method and Chen algorithm by distributed arithmetic method using ROM table instead of multiplier for design DCT module of high speed.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.24 no.3 s.174
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• pp.803-809
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• 2000

For the effective analysis of an engineering problem, meshless methods which require only positioning finite points without the element meshing recently have been proposed and being studied extensively. Meshless methods have difficulty in imposing essential boundary conditions directly, because non-interpolate shape functions originated from an approximation process are used. So some techniques, which are Lagrange multiplier method, modified variational principles and coupling with finite elements and so on, were introduced in order to impose essential boundary conditions. In spite of these methods, imposition of essential boundary conditions have still many problems like as non-positive definiteness, inaccuracy and negation of meshless characteristics. In this paper, we propose a new method which modifies shape function. Through numerical tests, convergence, accuracy and validity of this method are compared with the standard EFGM which uses Lagrange multiplier method or modified variational principles. According to this study, the proposed method shows the comparable accuracy and efficiency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.6
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• pp.813-818
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• 2021

This paper proposes an optimized hardware implementation method for existing CIE1931 color gamut control algorithm. Among the post-processing methods of dehazing algorithms, existing algorithm with relatively low computations have the disadvantage of consuming many hardware resources by calculating large bits using Split multiplier in the computation process. The proposed algorithm achieves computational reduction and hardware miniaturization by reducing the predefined two matrix multiplication operations of the existing algorithm to one. And by optimizing the Split multiplier computation, it is implemented more efficient hardware to mount. The hardware was designed in the Verilog HDL language, and the results of logical synthesis using the Xilinx Vivado program were compared to verify real-time processing performance in 4K environments. Furthermore, this paper verifies the performance of the proposed hardware with mounting results on two FPGAs.