• Journal of the Korean Mathematical Society
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• v.58 no.1
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• pp.91-107
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• 2021

A bounded linear operator T on a separable infinite dimensional Banach space X is called strongly hypercyclic if $$X{\backslash}\{0\}{\subseteq}{\bigcup_{n=0}^{\infty}}T^n(U)$$ for all nonempty open sets U ⊆ X. We show that if T is strongly hypercyclic, then so are Tn and cT for every n ≥ 2 and each unimodular complex number c. These results are similar to the well known Ansari and León-Müller theorems for hypercyclic operators. We give some results concerning multiplication operators and weighted composition operators. We also present a result about the invariant subset problem.

• The Journal of Information Technology
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• v.6 no.4
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• pp.11-23
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• 2003

We proposes that Design of the Digital Neuron Processor and Development of the Algorithm for the real time object recognition in the making Automatic system which uses the residue number system making the high speed operation possible without carry propagation, in this paper. Consisting of MAC(Multiplication and Accumulation) operator unit using Residue number system and sigmoid function operator unit using Mixed Residue Conversion is designed. The Designed circuits are descripted by C language and VHDL and synthesized by Compass tools. Finally, the designed processor is fabricated in 0.8${\mu}m$ CMOS process. Result of simulations shows that critical path delay time is about 19nsec and operation speed is 0.6nsec and the size can be reduced to 1/2 times co pared to the neural networks implemented by the real number operation unit. The proposed design the digital neuron processor can be implemented of the object recognition in the making Automatic system with desired real time processing.

• Smart Structures and Systems
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• v.14 no.6
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• pp.1131-1150
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• 2014

One of the issues in extending the range of applicable problems of real-time hybrid simulation is the computation speed of the simulator when large-scale computational models with a large number of DOF are used. In this study, functionality of real-time dynamic simulation of MDOF systems is achieved by creating a logic circuit that performs the step-by-step numerical time integration of the equations of motion of the system. The designed logic circuit can be implemented to an FPGA-based system; FPGA (Field Programmable Gate Array) allows large-scale parallel computing by implementing a number of arithmetic operators within the device. The operator splitting method is used as the numerical time integration scheme. The logic circuit consists of blocks of circuits that perform numerical arithmetic operations that appear in the integration scheme, including addition and multiplication of floating-point numbers, registers to store the intermediate data, and data busses connecting these elements to transmit various information including the floating-point numerical data among them. Case study on several types of linear and nonlinear MDOF system models shows that use of resource sharing in logic synthesis is crucial for effective application of FPGA to real-time dynamic simulation of structural response with time step interval of 1 ms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.10 s.340
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• pp.35-38
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• 2005

Treatise that see designed MDS block newly algorithm itself is concise and improve the speed of Twofish cryptographic algorithm that easy of implement is good but the processing speed has slow shortcoming than Rijndael cryptographic algorithm Problem of speed decline by a bottle-neck phenomenon of processing process existed as block that designed MDS block occupies critical path of Twofish cryptographic system Multiplication arithmetic that is used by operator in this MDS convex using LUT arithmetic and modulo-2 arithmetic speed decline and a bottle-neck phenomenon about MDS itself remove. Twofish cryptographic system including MDS block designed newly by these result confirmed that bing elevation of the processing speed about $10\%$ than existing Twofish cryptographic system.

• The Journal of Information Technology
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• v.8 no.3
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• pp.1-10
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• 2005

Cosine and Sine function is widely used for the arithmetic, translation, object drawing, Simulation and etc. of Computer Graphics in Natural Science and Engineering. In general, Cordic Algorithm is effective method since it has relatively small size and simple architecture on trigonometric function generation. However profitably it has those merits, the problem of operation speed is occurred. In graphic display system, the operation result of object drawing is quantized and has the condition that is satisfied with rms error less than 1. So in this paper, the proposed generator is composed of partition operation at each ${\pi}/4$ and basic Cosine, Sine function generator in the range of $0{\sim}{\pi}/4$ using the lower order of Tayler's series in an acceptable error range, that enlarge the range of $0{\sim}2{\pi}$ according to a definition of the trigonometric function for the purpose of having a high speed Cosine, Sine function generation. And, division operator using code partition for divisor three is proposed, the proposed function generator has high speed operation, but it has the problems in the other application parts with accurate results, is need to increase the speed of the multiplication.

• Bulletin of the Korean Mathematical Society
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• v.53 no.4
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• pp.1071-1085
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• 2016

For $b{\in}L^1_{loc}({\mathbb{R}}^n)$, let ${\mathcal{I}}_{\alpha}$ be the bilinear fractional integral operator, and $[b,{\mathcal{I}}_{\alpha}]_i$ be the commutator of ${\mathcal{I}}_{\alpha}$ with pointwise multiplication b (i = 1, 2). This paper shows that if the commutator $[b,{\mathcal{I}}_{\alpha}]_i$ for i = 1 or 2 is bounded from the product Morrey spaces $L^{p_1,{\lambda}_1}({\mathbb{R}}^n){\times}L^{p_2,{\lambda}_2}({\mathbb{R}}^n)$ to the Morrey space $L^{q,{\lambda}}({\mathbb{R}}^n)$ for some suitable indexes ${\lambda}$, ${\lambda}_1$, ${\lambda}_2$ and $p_1$, $p_2$, q, then $b{\in}BMO({\mathbb{R}}^n)$, as well as that the compactness of $[b,{\mathcal{I}}_{\alpha}]_i$ for i = 1 or 2 from $L^{p_1,{\lambda}_1}({\mathbb{R}}^n){\times}L^{p_2,{\lambda}_2}({\mathbb{R}}^n)$ to $L^{q,{\lambda}}({\mathbb{R}}^n)$ implies that $b{\in}CMO({\mathbb{R}}^n)$ (the closure in $BMO({\mathbb{R}}^n)$of the space of $C^{\infty}({\mathbb{R}}^n)$ functions with compact support). These results together with some previous ones give a new characterization of $BMO({\mathbb{R}}^n)$ functions or $CMO({\mathbb{R}}^n)$ functions in essential ways.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.1
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• pp.88-95
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• 2002

In recent years, the security of hardware and software systems is one of the most essential factor of our safe network community. As elliptic Curve Cryptosystems proposed by N. Koblitz and V. Miller independently in 1985, require fewer bits for the same security as the existing cryptosystems, for example RSA, there is a net reduction in cost size, and time. In this thesis, we propose an efficient hardware architecture of underlying field arithmetic processor for Elliptic Curve Cryptosystems, and a very useful method for implementing the architecture, especially multiplicative inverse operator over GF$GF (2^m)$ onto FPGA and futhermore VLSI, where the method is based on optimized unit operation components. We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed and inversion speed has been improved 150 times, 480 times respectively compared with the thesis presented by Sarwono Sutikno et al. [7]. The designed underlying arithmetic processor can be also applied for implementing other crypto-processor and various finite field applications.