• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.3
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• pp.69-78
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• 1998

This paper presented a method of extracting algorithm for Edge Multiple-Valued Decision Diagrams(EMVDD), a new data structure, from Binary Decision Diagram(BDD) which is resently using in constructing the digital logic systems based on the graph theory. We discussed the function minimization method of the n-variables multiple-valued functions and showed that the algorithm had the regularity with module by which the same blocks were made concerning about the schematic property of the proposed algorithm. We showed the EMVDD of Full Adder by module construction and verified the proposed algorithm by examples. The proposed method has the visible, schematical and regular properties.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2002.12a
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• pp.502-505
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• 2002

본 논문은 다치(MVL:Multiple Valued Logic) 신경망의 BP(Backpropagation) 학습 알고리즘을 이용하여 패턴 인식에 이용하는 방법을 제안한다. MVL 신경망을 이용하여 패턴 인식에 이용함으로서, 네트워크에 필요한 시간 및 기억 공간을 최소화할 수 있고 환경 변화에 적응할 수 있는 가능성을 제시하였다. MVL 신경망은 다치 논리 함수를 기반으로 신경망을 구성하였으며, 입력은 리터럴 함수로 변환시키고, 출력은 MIN과 MAX 연산을 사용하여 구하였고, 학습을 하기 위해 다치 논리식의 편 미분을 사용하였다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.295-308
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• 1986

This paper presents a method of constructing multiple-valued logic functions based on Galois field. The proposed algorithm assigns all elements in GF(2**m) to bit codes that are easily converted binary. We have constructed an adder and a multiplier using a multiplexer after bit code operation (addition, multiplication) that is performed among elements on GF(2**m) obtained from the algorithm. In constructing a generalized multiple-valued logic functions, states are first minimized with a state-transition diagram, and then the circuits using PLA widely used in VLSI design for single and multiple input-output are realized.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.6
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• pp.589-594
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• 1992

This paper offers the simplification method of Multiple-Valued logic function based on M-AND,M-OR, NOT operation presented by Lukasiewicz. First in performing the simplification the result is different by the method to arrange Cube, the method to find the most effective adjacent term if, most of all, important in simplification. According to this method, the two-variable multiple-valued logic function given by truth table is decomposed. The simplification method in this paper proves that the number of devices and cost is considerably reduced comparing with the existing method 141 to realize the same logic functions.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.6
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• pp.868-875
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• 1995

This paper presents a method of constructing the multiple-valued combinational logic systems(MVCLS) by decision diagram. The switching function truth table of MVCLS is transformed into canonical normal form of sum-of-products(SOP) with literals at first. Next, the canonical normal form of SOP is transfered into multiple-valued logic decision diagram(MVLDD). The selecting of variable ordering is very important in this stage. The MVLDDs are quite different from each other according to the variable ordering. Sometimes the inadequate variable ordering produces a very large size of MVLDD means the large size of circuit implementation. An algorithm for generating the proper variable ordering produce minimal MVLDD and an example shows the verity of the algorithm. The circuits are realized with T-gate acceording to the minimal MVLDD.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.275-278
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• 2003

This paper presents a full-adder using current-mode multiple valued logic CMOS circuits. This paper compares propagation delay, power consumption, and PDP(Power Delay Product) compared with conventional circuit. This circuit is designed with a samsung 0.35um n-well 2-poly 3-metal CMOS technology. Designed circuits are simulated and verified by HSPICE. Proposed full-adder has 2.25 ns of propagation delay and 0.21 mW of power consumption.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.43-53
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• 1997

In this paper, the optimal synthesis algorithm of multiple-valued logic circuits using universal logic modules (ULM) U$_{f}$ based on 3-variable ternary reed-muller expansions is presented. We check the degree of each varable for the coefficients of reed-muller expansions and determine the order of optimal control input variables that minimize the number of ULM U$_{f}$ modules. The order of optimal control input variables is utilized the realization of multiple-valued logic circuits to be constructed by ULM U$_{f}$ modules based on reed-muller expansions using the circuit cost matrix. This algorithm is performed only unit time in order to search for the optimal control input variables. Also, this algorithm is able to be programmed by computer and the run time on programming is O(p$^{n}$ ).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.11a
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• pp.278-281
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• 1999

In this paper, Squential circuit was implemented by decision diagram that can analyze and test large amount of functions easily. First of all, Memery device of multiple valued squential circuit was used D F/F, implemented with CMOS current mode. The opreation property of this circuit involved by PSPICE simulation. The result of Decision Diagram sequential circuit is simple and regular for selecting wire routing and posesses the property of analyze, testing. so it suitable for VLSI implementation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.4
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• pp.460-465
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• 1986

In this paper, a method for constructing of the sequential multiple-valued logic circuits over Galois field GF(px) is proposed. First, we derive the Talyor series over Galois field and the unique matrices which accords with the number of the element over the finite field, and we constdruct sequential multiple-valued logic circuits using these matrices. Computational procedure for traditional polynomial expansion can be reduced by using this method. Also, single and multi-input circuits can be easily implemented.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.6
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• pp.580-598
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• 1987

This paper presents a method to realize the sequential multiple-valued Logic on Galois field. First, We develop so that Taylor series can be corresponded the irreducible polynomial to realize over the finite field, and produce the matrix. This paper object expanded a basic concept of the conbinational Logic circuit so as to apply in the sequential Logic circuit. First of all, We suggest a theory for constructing sequential multiple-valued Logic circuit. Then, We realized the construction with the single input and the multi-output that expanded its function construction. In case of the multi-output, the circuit process by the partition function concept as the mutual independent. This method can be reduced a enormous computer course to need a traditional extention that designed the sequential multi-valued Logic circuit.