• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6A
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• pp.871-880
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• 1999

In this paper, a pseudo-noise(PN) tracking and demodulation circuits are analyzed and designed for a direct-sequence/spread-spectrum multiple access system under a mobile fading channel. We consider noncoherent delay locked loop(DLL) as a PN code tracking loop which has 1/8 PN chip resolution. The tracking performance of DLL is evaluated in terms of locking time from a loose state and tracking jitter. The received signal is demodulated to original data by despreading with PN code locked by DLL. Also the designed circuit supports sound service of 32Kbps and in-band signal with 4.096MHz chip clock. The circuits are implemented and verified with FPGA, which is shown completely data recovery under AWGN 7dB and will be available for IMT-2000.

• Sleep Medicine and Psychophysiology
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• v.3 no.2
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• pp.18-31
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• 1996

Jet-lag can be defined as the cumulative physiological and psychological effects of rapid air travel across multiple time zones. Many reports have suggested that age-related changes in sleep reflect fundamental changes in the circadian system and in significant declines in slow wave sleep. Jet lag is a dramatic situation in which the changes of the phase of circadian process and homeostatic process of sleep occur. Thus the authors evaluatead the changes of sleep-wake cycle from jet lag by age. Thirty-eight healthy travellers were studied for 3 days before and 7 days after jet-flights across seven to ten time zone. They were aged 19-70, They trareled eastbound, Seoul to North America (USA, Canada). Sleep onset time, wake-up time, sleep latency, awakening frequency on night sleep, awakening duration on night sleep, sleepiness at wake-up and nap length were evaluated. Our results suggest that by the 7 to 10 time zone shift, the old age group was significantly influenced in sleep-wake cycles. The date on which subjective physical condition was recovered was $6.23{\pm}83$ day after arrivals for old age group, while for young and middle age group, $4.46{\pm}1.50$ day and $4.83{\pm}1.52$ day, respectively. In old age group, sleep onset time was later than baselines and could not recover untill 7th day. But in other groups, the recovery was within 5th day. Nap dura fion was longer in old age group through jet lag than younger age group. In other parameters, there was no definite difference among three age groups. Our results suggested that the old age was significantly influenced by the disharmony between internal body clock and sleep-wake cycle needed at the travel site. Thus we proved that recovery ability from jet lag was age-dependent as well as travelling direction-dependent. To demonstrate more definite evidence, EEG monitoring and staging of sleep were funthun encouraged.

• The Bulletin of The Korean Astronomical Society
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• v.36 no.2
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• pp.122.2-122.2
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• 2011

For more than a decade, NEA (Near-Earth Asteroid) survey teams equipped with 1 meter-class telescopes discovered thousands of NEAs in the northern sky. As of August 2011, some 8,200 NEAs have been cataloged, yet only five percent of them has been investigated for their physical and chemical properties. In order to improve current situation, we propose a deep ecliptic survey utilizing KMTNet, for detection and characterization of NEAs in the southern sky. Thanks to the wide-field capability (four square degrees) of the telescopes, we will be able to considerably expand the search volume carrying out precision photometry down to 21.5th magnitude. We plan to focus our survey on opposition and two "sweet spots" in the ecliptic belt. Since SDSS colors characterize mineralogical properties of NEAs, g', r', i', z' filters will be employed. Based on the round-the-clock observation, we will study their rotational properties; for multiple systems, mass, density and other physical parameters can be obtained. We plan to maintain a dedicated database of the physical and mineralogical properties of NEAs. With this archive, it is expected that our understanding on the population will see a drastic change. We also plan to participate in the GAIA Follow-Up Network for ground based observation of the Solar System Objects (GAIA-FUN-SSO). The follow- up astrometry will be performed upon alerts issued by the GAIA-FUN-SSO Central Node in France.

• Journal of the Korea Society of Computer and Information
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• v.16 no.5
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• pp.1-11
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• 2011

As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements (PEs) and operates on a 3-stage pipelining. Experimental results indicated that the proposed parallel processor outperforms conventional parallel processors in terms of performance. In addition, our proposed parallel processor outperforms commercial high-performance TI C6416 DSP in terms of performance (1.4-31.4x better) and energy efficiency (5.9-8.1x better) with same 130nm technology and 720 clock frequency. The proposed parallel processor was developed with verilog HDL and verified with a FPGA prototype system.

• Journal of Positioning, Navigation, and Timing
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• v.5 no.4
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• pp.181-191
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• 2016

A Satellite Based Augmentation System (SBAS) provides differential correction and integrity information through geostationary satellite to users in order to reduce Global Navigation Satellite System (GNSS)-related errors such as ionospheric delay and tropospheric delay, and satellite orbit and clock errors and calculate a protection level of the calculated location. A SBAS is a system, which has been set as an international standard by the International Civilian Aviation Organization (ICAO) to be utilized for safe operation of aircrafts. Currently, the Wide Area Augmentation System (WAAS) in the USA, the European Geostationary Navigation Overlay Service (EGNOS) in Europe, MTSAT Satellite Augmentation System (MSAS) in Japan, and GPS-Aided Geo Augmented Navigation (GAGAN) are operated. The System for Differential Correction and Monitoring (SDCM) in Russia is now under construction and testing. All SBASs that are currently under operation including the WAAS in the USA provide correction and integrity information about the Global Positioning System (GPS) whereas the SDCM in Russia that started SBAS-related test services in Russia in recent years provides correction and integrity information about not only the GPS but also the GLONASS. Currently, LUCH-5A(PRN 140), LUCH-5B(PRN 125), and LUCH-5V(PRN 141) are assigned and used as geostationary satellites for the SDCM. Among them, PRN 140 satellite is now broadcasting SBAS test messages for SDCM test services. In particular, since messages broadcast by PRN 140 satellite are received in Korea as well, performance analysis on GPS/GLONASS Multi-Constellation SBAS using the SDCM can be possible. The present paper generated correction and integrity information about GPS and GLONASS using SDCM messages broadcast by the PRN 140 satellite, and performed analysis on GPS/GLONASS Multi-Constellation SBAS performance and APV-I availability by applying GPS and GLONASS observation data received from multiple reference stations, which were operated in the National Geographic Information Institute (NGII) for performance analysis on GPS/GLONASS Multi-Constellation SBAS according to user locations inside South Korea utilizing the above-calculated information.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.5_6
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• pp.257-266
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• 2007

In On-Chip bus, the arbitration scheme is one of the critical factors that decide the overall system performance. The arbitration scheme used in traditional shared bus is the master-side arbitration based on the request and grant signals between multiple masters and single arbiter. In the case of the master-side arbitration, only one master and one slave can transfer the data at a time. Therefore the throughput of total bus system and the utilization of resources are decreased in the master-side arbitration. However in the slave-side arbitration, there is an arbiter at each slave port and the master just starts a transaction and waits for the slave response to proceed to the next transfer. Thus, the unit of arbitration can be a transaction or a transfer. Besides the throughput of total bus system and the utilization of resources are increased since the multiple masters can simultaneously perform transfers with independent slaves. In this paper, we implement and analyze the arbitration schemes for the Multi-Layer AHB BusMatrix based on the slave-side arbitration. We implement the slave-side arbitration schemes based on fixed priority, round robin and dynamic priority and accomplish the performance simulation to compare and analyze the performance of each arbitration scheme according to the characteristics of the master and slave. With the performance simulation, we observed that when there are few masters on critical path in a bus system, the arbitration scheme based on dynamic priority shows the maximum performance and in other cases, the arbitration scheme based on round robin shows the highest performance. In addition, the arbitration scheme with transaction based multiplexing shows higher performance than the same arbitration scheme with single transfer based switching in an application with frequent accesses to the long latency devices or memories such as SDRAM. The improvements of the arbitration scheme with transaction based multiplexing are 26%, 42% and 51%, respectively when the latency times of SDRAM are 1, 2 and 3 clock cycles.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.12C
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• pp.1288-1298
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• 2002

To implement elliptic curve cryptosystem in GF(2$\^$m/) at high speed, a fast divider is required. Although bit-parallel architecture is well suited for high speed division operations, elliptic curve cryptosystem requires large m(at least 163) to support a sufficient security. In other words, since the bit-parallel architecture has an area complexity of 0(m$\^$m/), it is not suited for this application. In this paper, we propose a new serial-in serial-out systolic array for computing division operations in GF(2$\^$m/) using the standard basis representation. Based on a modified version of tile binary extended greatest common divisor algorithm, we obtain a new data dependence graph and design an efficient bit-serial systolic divider. The proposed divider has 0(m) time complexity and 0(m) area complexity. If input data come in continuously, the proposed divider can produce division results at a rate of one per m clock cycles, after an initial delay of 5m-2 cycles. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. Since the proposed divider can perform division operations at high speed with the reduced chip area, it is well suited for division circuit of elliptic curve cryptosystem. Furthermore, since the proposed architecture does not restrict the choice of irreducible polynomial, and has a unidirectional data flow and regularity, it provides a high flexibility and scalability with respect to the field size m.