• Journal of Korea Multimedia Society
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• v.15 no.1
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• pp.81-86
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• 2012

This paper presents a VLSI design for lifting-based discrete wavelet transform (DWT) 9/7 filter using multiplierless multiple constant multiplication (MCM) architecture. This proposed design is based on the lifting scheme using pattern search for folded architecture. Shift-add operation is adopted to optimize the multiplication process. The conventional serial operations of the lifting data flow can be optimized into parallel ones by employing paralleling and pipelining techniques. This optimized design has simple hardware architecture and requires less computation without performance degradation. Furthermore, hardware utilization reaches 100%, and the number of registers required is significantly reduced. To compare our work with previous methods, we implemented the architecture using Verilog HDL. We also executed simulation based on the logic synthesis using $0.18{\mu}m$ CMOS standard cells. The proposed architecture shows hardware reduction of up to 60.1% and 44.1% respectively at 200 MHz clock compared to previous works. This implementation results indicate that the proposed design performs efficiently in hardware cost, area, and power consumption.

• Journal of the Korea Computer Graphics Society
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• v.19 no.4
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• pp.1-11
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• 2013

In this paper, we represented the HTML5 webpage in 3D space for the 3D stereoscopic display by using CSS3 stylesheet; browser-based declarative contents, and proposed CSS Stereo 3DTV Profile. First, we suggested various webpage separation methods for reconstructing webpages in the 3D space effectively. Next, we suggested 3D view volume setting method by using extended CSS3 modules. And then, pre-processor converts sample contents which is written extended CSS stylesheet into the present CSS stylesheet for displaying in the webkit based browser. For the resulting stereoscopic images, we developed a rendering engine emulator which is implemented in JavaScript for simple display in the web browser, which produced dual images from virtual left and right-eyed cameras. And we have checked the sample contents displayed on the 3DTV.

• Journal of Korea Multimedia Society
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• v.3 no.3
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• pp.263-271
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• 2000

In this paper, an acoustic echo canceller(AEC) is implemented by ADSP-2181. This AEC uses a noise robust adaptive algorithm and a postprocessing method which attenuates residual echo using cross-correlation between estimated error signal and microphone input signal. We propose new postprocessing method that uses two thresholds to prevent signal distortion after postprocessing and to improve the performance of AEC without extra computational burden. Through experiments using a 16 bit fixed-point DSP board (ADSP-2181 EZ-KIT Lite board), it is shown that the noise robust adaptive algorithm performs well in the double-talk situations and the convergence speed is comparable to NLMS. Using the postprocessor, ERLE is improved about 20 dB. As a result, the AEC with a postprocessor shows better performance than conventional ones.

• Journal of Korea Multimedia Society
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• v.14 no.1
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• pp.76-84
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• 2011

Embedded Systems need to ensure real-time of the task response time depending on the applied fields of it. And task could be faulty due to various reasons in real time systems. Therefore in this paper, we design a task scheduler that guarantees deadlines of periodic tasks and considers a fault tolerance of defective task in embedded system with a single processor. In order to provide real-time, we classify tasks with periodic/aperiodic tasks and applies RMS(Rate Monotonic Scheduling) method to schedule periodic tasks and can guarantees execution of aperiodic tasks by managing surplus times obtained after analyzing the execution time of periodic tasks. In order to provide fault tolerance, we manage backup times and reexecute a fault task to restore it's conditions.

• Journal of Korea Multimedia Society
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• v.9 no.4
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• pp.388-400
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• 2006

There are wireless location acquisition technique, LBS platform technique, and LBS application technique in the important technical elements of the LBS. In this paper, we design a location data management system which is the core base technique of the important technical elements of the LBS. The proposed system consist of an application interface of LBS, a query processor of application. service, a location estimator of the moving objects, a location information manager, a real-time data receiver, and a database of location data. This system manages efficiently the location change information of the moving objects using the database technique, suggests some useful inform to the users of LBS, and supports operation and facility of location estimation to process continuous location data of the moving objects. On the basis of location data triggering, this system supplements the problem of the related location data management systems to complement the loss of location data in the environment of real-time.

• Journal of Korea Multimedia Society
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• v.18 no.6
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• pp.723-733
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• 2015

High availability is of utmost importance in real-time embedded systems. Temporary failures due to software or hardware faults should not result in a system crash. To achieve high availability, embedded systems typically use a combination of hardware and software techniques. A watchdog timer is a hardware component in embedded microprocessors that can be used to automatically reset the processor if software anomalies are detected. The embedded system relies on a single watchdog timer, however, can be permanently disabled if the timer is not properly configured, e.g. falling into an indefinite loop. STM32F4 provides two different types of watchdog timer in terms of timing accuracy and robustness. In this paper, we propose a hybrid approach, called long-tail watchdog timer, to utilize both timers to achieve self-reliance in embedded systems even though one of timers fails. Experimental results confirm that the proposed approach successfully handles various failure scenarios and present performance comparisons between single watchdog timer and hybrid approach in terms of configuration parameters of watchdog timers in STM32F4, counter value and window size.

• Journal of Korea Multimedia Society
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• v.14 no.3
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• pp.462-470
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• 2011

Retargetability is typically achieved by providing target machine information, ADL, as input. The ADL are used to specify processor and memory architectures and generate software toolkit including compiler, simulator, etc. Simulator are critical components of the exploration and software design toolkit for the system designer. They can be used to perform diverse tasks such as verifying the functionality and/or timing behavior of the system, and generating quantitative measurements(e.g., power energy consumption) which can be used to aid the design process. In this paper, we generate the energy consumption estimation simulator through ADL. For this goal, firstly, we describes the energy consumption estimation and monitoring informations on the ADL based on EXPRESSION. Secondly, we generate the energy estimation and monitoring simulation library and then constructs the simulator, RenergySim. Lastly, we represent the energy estimations results for MIPS R4000 ADL description. From this subjects, we contribute to the efficient architecture developments and prompt SDK generation through programmable experiments in the field of mobile software development.

• Journal of Korea Multimedia Society
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• v.14 no.3
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• pp.368-377
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• 2011

This paper explains the hardware structure of SURF(Speeded Up Robust Feature) based feature point extractor and its FPGA verification result. SURF algorithm produces novel scale- and rotation-invariant feature point and descriptor which can be used for object recognition, creation of panorama image, 3D Image restoration. But the feature point extraction processing takes approximately 7,200msec for VGA-resolution in embedded environment using ARM11(667Mhz) processor and 128Mbytes DDR memory, hence its real-time operation is not guaranteed. We analyzed integral image memory access pattern which is a key component of SURF algorithm to reduce memory access and memory usage to operate in c real-time. We assure feature extraction that using a Vertex-5 FPGA gives 60frame/sec of VGA image at 100Mhz.

• Journal of Korea Multimedia Society
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• v.13 no.1
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• pp.30-37
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• 2010

Many embedded real - lime systems have adopted processors supported with dynamic voltage scal-ing(DVS) recently. Power is one of the important metrics for Optimization in the design and operation of embedded real-time systems. We can save considerable energy by using slowdown of processor sup-ported with DVS. In this paper, we improved the previous algorithm at a point of view of time complexity to calculate task slowdown factors for an efficient energy consumption in embedded real-time systems with task synchronization. We grasped the properties of the previous algorithm having $O(n^{2})$ time complexity through mathematical analysis and s simulation. Using its properties we proposed the improved algorithms with O(nlogn) and O(n) time complexity which have the same performance as the previous algorithm has.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.345-348
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• 2013

This paper provides a method for compression and transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively.