References
- Prabhat Mishra and Nikil Dutt, Processor Description Languages, Morgan Kaufmann, 2008.
- Rainer Leupers, "Code Generation for Embedded Processor," ISSS;00: 13th International System Synthesis Symposium, pp.173-178, Sep. 2000.
- A. Hoffman and H. Meyr, R. Leupers, Architecture Exploration for Embedded Processors with LISA, Kluwer Academic Publishers (ISBN: 1-4020-7338-0), Dec. 2002.
- Uli Kremer, "Compilers for Power and Energy Management," PLDI'03: ACM SIGPLAN 2003 conference on Programming Language Design and Implementation Tutorial, 2003.
- Uli Kremer, "Low Power/Power Compiler Optimizations," in Low-Power Electronics Design(Editor: Christian Piguet), CRC Press, 2005.
- A. Parikh, Soontae Kim, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin, "Instruction Scheduling for Low Power," Journal of VLSI Signal Processing, Vol.37, pp.129-149, 2004. https://doi.org/10.1023/B:VLSI.0000017007.28247.f6
- Eric C. Schnarr, Mark D. Hill, and James R. Larus, "Facile: A Language and Compiler for High-Performance Processor Simulators," PLDI'99: Proceedings of the ACM SIGPLAN 1999 conference on Programming Language Design and Implementation, pp.1-11, 1999.
- Mehrdad Reshadi, Nikhil Bansal, Prabhat Mishra, and Nikill Dutt, "An Efficient Retargetable framework for Instruction-Set Simulation," CODES+ISSS'03: Proceedings of the International Symposium on Hardware/ Software Codesign and System Synthesis, pp. 13-18, 2003.
- R. Leupers, J. Elste, and B. Landwehr, "Generation of Interpretive and Compiled Instruction Set Simulators," ASP-DAC'99: Proceeding of the Asia South Pacific Design Automation Conference 1999, 1999.
- Alex Nicolau, et al., "V-SAT: A Visual Specification and Analysis Tool for System- on-Chip Exploration," Journal of System Architecture, Vol. 47, pp.263-275, 2001. https://doi.org/10.1016/S1383-7621(00)00049-7
- Jianwen Zhu and Daniel D. Gasski, "A Retargetable, Ultra-fast Instruction Set Simulator," DATE'99: Proceedings of the Design Automation and Test conference in Europe, p. 1999.
- A. Nohl, et al., "A Universal Technique for Fast and Flexible Instruction-set Architecture Simulation," In Proc. of DAC, 2002.
- M. Reshadi, et al., "Instruction Set Compiled Simulation: A Technique for Fast and Flexible Instruction-set Simulation," In Proc. of DAC, 2003.
- Anupam Chattopadhyay, Heinrich Meyr, and Rainer Leupers, "LISA: A Uniform for Embedded Processor Modeling, Implementation, and Software Toolsuite Generation," Processor Description Languages: Chap. 5, Morgan Kauffman, 2008.
- Prabhat Mishra, Aviral Shrivastava, and NiKill Dutt, "Architecture Description Language-driven Software Toolkit Generation for Architectural Exploration of Programmable SOCs," ACM Transactions on Design Automation of Electronics Systems, Vol.11, No.2, pp.626-658, 2006. https://doi.org/10.1145/1142980.1142985
- Wissam Chedid and Chansu Yu, "Survey on Power Management Techniques for Energy Efficient Computer Systems," Technical Report: CSU-ECE-TR-02-01, Cleveland State University, 2002.
- SimpleScalar: MASE. http://www.simplescalar.com
- W. Ye, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, "The Design and Use of SimplePower: A Cycle Accurate Energy Estimation Tool," DAC'00: Proceedings of the 37th Design Automation Conference, pp.340-345, 2000.
- D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A Framework for Architectural-Level Power Analysis and Optimizations," In Proc. of International Symposium on Computer Architecture, pp.83-94, 2000.
- Sim-Panalyzer(ver 2.0.3) reference Manual. http://www.eecs.umich.edu/-panalyzer/.
Cited by
- Study on the Obsolescence Forecasting Judgment of PV Systems adapted Micro-inverters vol.18, pp.7, 2015, https://doi.org/10.9717/kmms.2015.18.7.864