• IEIE Transactions on Smart Processing and Computing
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• v.6 no.4
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• pp.292-298
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• 2017

The complexity of image compression algorithms has increased in order to improve image compression efficiency. One way to resolve high computational complexity is parallel processing. However, entropy coding, which is lossless compression, does not fit into the parallel processing form because of the correlation between consecutive symbols. This paper proposes a new application-specific instruction set processor (ASIP) platform by adding new context-adaptive binary arithmetic coding (CABAC) instructions to the existing platform to quickly process a variety of entropy coding. The newly added instructions work without conflicts with all other existing instructions of the platform, providing the flexibility to handle many coding standards with fast processing speeds. CABAC software is implemented for High Efficiency Video Coding (HEVC) and the performance of the proposed ASIP platform was verified with a field programmable gate array simulation.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.08a
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• pp.165-168
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• 1998

제안하고 있는 CSD17C00 chip은 C&S technology에서 개발한 것으로, 음성 신호 처리를 위해 범용으로 구현되었으며, 16 bit 40 MIPS DSP group OAK DSP Core를 포함, 이에 Miscellaneous Logic, Serial Port, Host Interface, Timer, Compander 의 5가지 Peripherals 과 범용 I/O Ports 로 설계되었다. 1차적으로 CSD17C00 Chip 의 성능을 점검하였다. 그 결과, 응용 프로그램은 28MIPS의 계산속도를 갖으며, 프로그램 ROM 크기는 8.85KWords 이고, 10KWords 의 데이터 ROM 과 4KWords 데이터 RAM을 필요로 한다. CSD17C00 CHIP은 멀티미디어 통신용 VOCODER 개발을 위한 범용성을 갖추고 있으며, VOCODER 용 S/W 개발 환경 및 H/W 구조가 여타 범용 DSP에 비해편의성고 K합리성을 제공하도록 설계되어 있다. 따라서, 이를 이용한다면, 멀티 미디어 통신용 VOCODER, INTERNET PHONE CO-PROCESSOR, DIGITAL RECODER, MPEG AUDIO ENCODER & DECODER 등 다양한 제품으로의 응용이 가능할 것으로 전망된다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.229-234
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• 2007

In this paper, we present an efficient instruction set architecture using vector register file hardware to accelerate operation of general matrix-vector operations in DSP microprocessor. The technique enables in-situ row-access as well as column access to the register files. It can reduce the number of memory access significantly. The technique is especially useful for block-based video signal processing kernels such as FFT/IFFT, DCT/IDCT, and two-dimensional filtering. We have applied the new instruction set architecture to in-loop deblocking filter processing in H.264 decoder. Performance comparisons show that the required load/store operations for the in-loop deblocking filter can be reduced about 42%. The architecture would improve the processing speed, and code density in DSP microprocessor especially for video signal processing substantially.

• Journal of information and communication convergence engineering
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• v.8 no.6
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• pp.640-644
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• 2010

When we talk with hands-free in a car or noisy lobby, the performance of the echo canceller degrade because background noise added to echo caused by the distance from mouth to microphone is relatively long. It gives a reason for necessity of noise-robust and high convergence speed adaptive algorithm. And if acoustic echo canceller operated not perfectly, residual signal going through the echo canceller to far-end speaker remains residual echo, which degrade quality of talk. To solve this problem, post-processing needed to remove residual echo ones more. In this paper, we propose a new acoustic echo canceller, which has noise robust and high convergence speed, linked with linear predictor as a post-processor. By computer simulation, it is confirmed that the proposed algorithm shows better performance from acoustic interference cancellation (AIC) viewpoint.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.86-88
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• 2000

멀티미디어 태스크는 기존 범용 운영 체제의 시분할 스케줄러에서 만족시킬 수 없는 시간적 요구사항을 가진다. 이런 태스크를 기존의 시분할 태스크와 함께 서비스하기 위해서는 새로운 스케줄링 프레임워크가 필요하다. FQ(Fair Queueing)은 태스크의 공유비율에 비례하여 자원을 할당하는 방법으로 이질적인 태스크(멀티미디어 태스크, 일반 시분할 태스크)가 공존하는 개방적인 환경에서의 스케줄링 정책으로 적합하다는 특징이 있다. 본 논문에서는 FQ의 종류인 WFQ(Weighted Fair Queueing)를 개선하여 하나의 스케줄러에서 다른 두 부류의 태스크를 모두 처리하는 요구비율 기반의 프로세서 예약 기법을 제안한다. 실시간 태스크와 시분할 태스크를 처리하기 위해서 실시간 부류의 태스크를 우선적으로 배치하고, 실시간 부류 태스크의 실행 사이에 시분할 태스크를 스케줄하여 실시간 태스크에 대해서 보장된 서비스를, 시분할 태스크에 대해서는 이 태스크에 할당된 예약만큼의 프로세서 시간을 제공한다. 모의 실험에서는 제안한 프로세서 예약 방식이 실시간 태스크와 시분할 태스크를 효율적으로 처리하며 기존의 WFQ보다 더 안정적임을 보인다.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1823-1826
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• 2002

On modern computer culture, the high quality data is required in multimedia systems. So, the technology of data compression fur data transmission is necessary now. This paper presents the pipeline architecture for the low and column address generator of 2D DCT/IDCT (Discrete Cosine Transform/Inverse Discrete Cosine Transform. In the proposed architecture, the area of hardware is reduced by using the DA (distributed arithmetic) method and applies the concepts of pipeline to the parallel architecture. As a result the designed pipeline of the low and column address generator for 2D DCT/IDCT architecture is implemented with an efficiency and high speed compared with the non-pipeline architecture.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.1023-1024
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• 2015

This paper propose the method of constructing the improved hardware arithmetic operation unit over galois fields. The proposed the hardware arithmetic operation unit have advantage which is more regularity and extensibility compare with earlier method. Also it is able to apply to any multimedia hardware which is the basic arithmetic operation unit. For the future we will research the processor which is the processing arithmetic and logical operation.

• ETRI Journal
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• v.32 no.4
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• pp.540-547
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• 2010

One of the critical issues in on-chip serial communications is increased power consumption. In general, serial communications tend to dissipate more energy than parallel communications due to bit multiplexing. This paper proposes a low-power bus serialization method. This encodes bus signals prior to serialization so that they are converted into signals that do not greatly increase in transition frequency when serialized. It significantly reduces the frequency by making the best use of word-to-word and bit-by-bit correlations presented in original parallel signals. The method is applied to the revision of an MPEG-4 processor, and the simulation results show that the proposed method surpasses the existing one. In addition, it is cost-effective when implemented as a hardware circuit since its algorithm is very simple.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.856-859
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• 2005

This paper presents a method of constructing the highly efficiency arithmetic operation unit systems(AOUS) based on fields. The proposed AOUS is more regularity and extensibility than previous methods. Also, the proposed AOUS be able to apply basic multimedia hardware. The future research is demanded to more compact and advanced arithmetic operation algorithm.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10a
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• pp.508-510
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• 2001

본 XSLT 처리기는 객체모델링 기법인 UML을 기반으로 설계하였고 핵심적인 부분은 XSL 스타일 시트를 HTML 패스/스타일로부터 구성해 내는 것이다 즉 문서 작성자는 XML문서를 작성하고 파싱하여 패스 테이블을 형성하고 이 패스 테이블에 작성자는 HTML패스/스타일을 추가한다. 이를 통해 XSL의 복잡한 스타일에 대한 고려없이 문서구조와 정보에 집중하여 견고한 문서를 만들 수 있다. 즉 구조 문서인 XML과 콘텐츠 타인의 대중적인 문서형인 HTML을 이용함으로써 적은 비용으로 다양한 문서 스타일을 구성할 수 있게 하여 XML 기술을 쉽게 보급시키며 컴포넌트 제작을 통해 다른 산업영역 문서교환에서 활용할 수 있다.