• Proceedings of the Korean Information Science Society Conference
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• 1999.10b
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• pp.265-267
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• 1999

XML 언어로 설계된 SMIL(Synchronized Multimedia Integration Language)은 멀티미디어 객체들의 순차적 혹은 병렬적 동기화를 효율적으로 할 수 있는 마크업 언어로써, web을 이용한 원격 강의나 홍보 등을 더욱 생성하고 dynamic하게 보여 줄 수 있어, 그 사용이 확대될 전망이다. 본 논문에서는 각종 웹 단말기에 손쉽게 embedding 될 수 있는 SMIL 프로세서에 대한 설계가 제안된다. 웹 응용을 위해, 속도의 개선과 시스템 독립적인 function들로 구성되는 parser와 응용에 적합한 API의 설계에 주안점을 두었으며, 추후 XML parser function들과 API 설계를 위해 가능한 적은 수정을 통하여 재사용이 가능하도록 하는데 또한 주안점을 두고 있다.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.226-229
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• 2000

In this paper, we describe implementation of 32-Bit RISC Core for portable communication/information equipment, such as cellular telephones and personal digital assistants, notebook, etc. The RISC core implements the ARM$\^$R/V4 instruction set on the basis of low power techniques in architecture level and logic level. It operates with 5-stage pipeline, and has harvard architecture to increase execution speed. The processor is modeled and simulated in RTL level using VHDL. Behavioral Cache and MMU are added to the VHDL model for instruction level verification of the processor. The core is implemented using Mentor P'||'&'||'R tools with IDEC C-631 Cell library of 0.6$\mu\textrm{m}$ CMOS 1-poly 3-metal CMOS technology.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.585-588
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• 2004

This paper describes design and verification of the motion estimation and compensation unit using full search algorithm. Video processor is the key device of video communication systems. Motion estimation is the key module of video processor. The technologies of motion estimation and compensation unit are the core technologies for wireless video telecommunications system, portable multimedia systems. In this design, Verilog simulator and logic synthesis tools are used for hardware design and verification. In this paper, motion estimation and compensation unit are designed using FPGA, coded in Verilog HDL, and simulated and verified using Xilinx FPGA.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.831-834
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• 1998

This paper describes a bus interface unit which is used in a 32bit high-performance multimedia RISC CPU including DSP unit. The main idea adopted in designing is that the bus interface unit enables the processor to provide on-chip functions for controlling memory and peripheral devices, including RAS-cAS multiplexing, DRAM refresh and parity generation and checking. The number of bus cycles used for a memory or I/O access is also defined by the processor, thus, no external bus controllers are required. All memories and peripheral devices can be connected directly, pin to pin, without any glue logic. That is the key point of the design.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.867-870
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• 2003

본 논문은 멀티미디어 데이터 처리를 위한 효율적인 RISC 프로세서 유닛의 설계를 목표로 Vector 프로세서의 SIMD(Single Instruction Multiple Data) 개념을 바탕으로 고정된 연산기 데이터 비트 수에 비해 상대적으로 작은 비트수의 데이터 연산의 부분 병렬화를 통하여 멀티미디어 데이터 연산의 기본이 되는 곱셈누적(MAC : Multiply and Accumulate) 연산의 성능을 향상 시킨다. 또한 기존의 MMX나 VIS 등과 같은 범용 프로세서들의 부분 병렬화를 위해 전 처리 과정의 필요충분조건인 데이터의 연속성을 위해 서로 다른 길이의 데이터 흑은 비트 수가 작은 멀티미디어의 데이터를 하나의 데이터로 재처리 하는 재정렬 혹은 Packing/Unpacking 과정이 성능 전체적인 성능 저하에 작용하게 되므로 본 논문에서는 기존의 프로세서의 연산기 구조를 재이용하여 병렬 곱셈을 위한 연산기 구조를 구현하고 이를 위한 데이터 정렬 연산 구조를 제안한다.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.4
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• pp.231-241
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• 2011

Recently, system virtualization has been applied to consumer electronics (CE) such as smart mobile phones. Although multi-core processors have become a viable solution for complex applications of consumer electronics, the issue of utilizing multi-core resources in the virtualization layer has not been researched sufficiently. In this paper, we present a new hypervisor design and implementation for multi-core CE devices. We concretely describe virtualization methods for a multi-core processor and multi-core-related subsystems. We also analyze bottlenecks of network performance in a virtualization environment that supports multimedia applications and propose an efficient virtual interrupt distributor. Our new multi-core hypervisor improves network performance by 5.5 times as compared to a hypervisor without the virtual interrupt distributor.

• Journal of Korea Society of Industrial Information Systems
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• v.8 no.2
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• pp.38-44
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• 2003

In this paper, we propose the method in which multimedia data simultaneously transfers to the main memory and the multimedia processor from the network interface card to improve bottleneck of system bus through analysis for architecture of video conference system and input/output model. The proposed method can reduce the number of system bus accesses, bus cycles, data transmission time and compression ratio of video data in the video conference system. We compared the performance between the proposed method and the conventional methods in the multi-party video conference systems. The simulation results showed that the proposed method was reduced the transmission time of multimedia data than the conventional method.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.1
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• pp.199-206
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• 2013

Recently, the diverse needs of the drivers for in-vehicle infotainment systems are increasing rapidly. As a result, the infotainment systems are equipped with more convenient and human-friendly high-tech features. In this paper, we designed and implemented in-vehicle multimedia infotainment system based on embedded system that was applied various multimedia to in-vehicles. The proposed system can support independent display on each screen for the multi-channel multimedia source based on one processor(1 CPU). Therefore, our system can be reduced costs compared to other systems. This system not only displays the video and audio data in storage devices but also displays CAM, T-DMB, and DVB-T multimedia contents which are supplied in real-time services. Also, our system could multi-screen displays multimedia data in smart phone using Wi-Fi. We expect that in-vehicle infotainment systems like AVN(Audio video navigation) and RSE(Rear Seat Entertainment) could be used in various applications and reduced costs.

• Journal of information and communication convergence engineering
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• v.6 no.3
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• pp.285-288
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• 2008

Most of multimedia processors for 2D/3D graphics acceleration use a lot of integer/floating point arithmetic units. We present a new architecture with an efficient ALU, built in a smaller chip size. It reduces instruction cycles significantly based on a foundation of multi-thread operation, variable length instruction words, dual phase operation, and phase instruction's coordination. We can decrease the number of instruction cycles up to 50%, and can achieve twice better performance.

• 한국정보통신설비학회:학술대회논문집
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• 2003.08a
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• pp.129-133
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• 2003

본 논문에서는 이동통신 System의 시험 및 운영단계에서 발생하는 불량원인 및 불필요한 업무공정을 $6{\sigma}$ 기법을 사용하여 개선 방안을 찾아내고 효과적인 업무 Processor를 확립 하였다.