• Title/Summary/Keyword: Multimedia Architecture

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Implementation of Shared Work Environment using JAVA on the CORBA Environment (CORBA 환경에서 JAVA를 이용한 공동 작업 환경 구현)

  • 김근형;이봉환
    • Proceedings of the Korea Multimedia Society Conference
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    • 1998.10a
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    • pp.208-213
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    • 1998
  • 멀티미디어 회의, 원격 교육, 원격 의료 등과 같이 다수가 참여하여 공동으로 작업을 하는 응용 서비스들이 컴퓨터와 네트워크의 발전에 따라 가능해지고 있다. 이와 같이 다수가 참여하여 객체를 공유하면서 공동 작업을 하여야 하는 응용들은 공유 작업 환경(shared work environment)을 필수적으로 요구한다. 또한 네트워크에서 다양한 응용 서비스들을 제공하고 관리하기 위해서는 서비스 세션에 대한 관리도 필요하다. 본 논문에서는 사용자가 여러 세션에 참여하여 공동 작업이 가능한 공유 작업 환경을 다자간 멀티미디어 서비스 세션의 제공, 제어 및 관리를 위한 메커니즘을 제공하는 CORBA(Common Object Request Broker Architecture)기반의 COMUS(CORBA based Multiparty Multimedia System)와 자바 언어의 객체 지향 특성을 이용하여 구현하였다.

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A Study on Highly Performance Multimedia Processor Architecture (고효율 멀티미디어 프로세서 아키텍쳐에 관한 연구)

  • 박춘명
    • Proceedings of the Korea Multimedia Society Conference
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    • 2001.06a
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    • pp.12-15
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    • 2001
  • 본 논문에서는 고효율 멀티미디어 프로세서 아키텍쳐에 대해 논의하였다. 제안한 멀티미디어 프로세서 아케텍쳐는 제안한 방법은 기존의 멀티미디어 프로세서의 단점들인 각종 텍스트, 사운드, 비디오 등의 미디어 들을 1개의 칩 속에서 처리할 수 있도록 하였으며, 또한 멀티미디어의 특성인 상호대화식 처리도 가능하게 하였다. 특히, 완전한 그래프에 기반을 둔 네트워크를 지향하므로 소프트웨어 없이 메모리 맵의 노드어드레싱을 가능하게 하였으며, 데이터 형태에 의존하는 완전한 재구성이 가능하며 동기/비동기를 갖는 시간 공유와 공간 공유 처리가 가능하다. 또한, 연속적임과 동적인 매체 데이터의 버스 충돌을 방지할 수 있으며 지역적임과 전반적인 공유 메모리 구조로부터의 버스 충돌도 방지할 수 있으며, 또한 가상현실과 흔합현실에도 적용할 수 있으리라 사료된다.

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Superscalar RISC Microprocessor Architecture with enhanced Multimedia Instructions (멀티미디어 명령어를 강화한 수퍼스칼라 RISC 마이크로프로세서 구조)

  • 이용환;문병인;이용석
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.931-934
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    • 1999
  • For applications in multimedia to which genuine RISC microprocessors are not suitably applicable, a new generation of fast and flexible microprocessors is required. In this paper, as a technique of integrating DSP functionality in a general RISC processor, a RISC that can execute DSP extension instructions is developed to improve the performance of multimedia application execution. This processor can execute DSP instructions in parallel with the execution of ALU instructions for efficient and fast execution. In addition, the execution ability of integer instructions is improved by enhancing the RISC core itself.

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Design of A Smart Fruit Quality Classification Platform Architecture (스마트 과일 품질 선별 플랫폼 구조 설계)

  • Choi, Han Suk;Cho, Je-Bong;Choi, Seung-young
    • Proceedings of the Korea Contents Association Conference
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    • 2017.05a
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    • pp.97-98
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    • 2017
  • 본 연구에서는 스마트 과일 품질 선별 플랫폼 구조를 제안한다. 스마트 과일 품질 선별 플랫폼 구조는 과일 내부 품질을 결정하는 주요 성분인 당도, 산도, 수분 등을 실시간으로 측정할 수 있는 분광 분석기와 과일의 외부 크기(부피), 색깔, 무게, 흠집 등을 처리할 수 있는 외부 품질 측정기로 구성된다.

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Design of an Architecture for Massively Multiplayer Online Game Server using Multimedia Storage Server (Multimedia Storage Server를 응용한 MMO 게임 서버 구조에 대한 설계)

  • 황요한;김동균;장인걸;신동일;김동현
    • Proceedings of the Korean Information Science Society Conference
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    • 2002.10d
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    • pp.211-213
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    • 2002
  • 온라인 게임(online game)은 초고속 통신망의 보급과 기존의 1인용 게임(Single-player game)의 인공지능에서 느낄 수 없었던 즐거움을 제공함으로써 급속도로 보급되었다. 또한 최근의 온라인 게임 시장은 그래픽 기술을 비롯한 하드웨어의 발달로 2D에서 3D로 옮겨가고 있다. 따라서 이러한 추세에 따라 온라인 게임은 보다 많은 멀티미디어 데이터를 필요로 하게 되었다. 이에 Multimedia Storage Sever를 멀티플레이어 온라인 게임(Multi-player online game)에 적용함으로써 보다 효율적인 멀티플레이어 온라인 게임 서버를 구성하고자 한다.

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A Design of Real-time VOD Server Simulator (실시간 VOD 서버 시뮬레이터 설계)

  • 정지영;김성수
    • Journal of the Korea Society for Simulation
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    • v.9 no.3
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    • pp.65-75
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    • 2000
  • In recent years, significant advances in computers and communication technologies have made multimedia services feasible. As a result, various queuing models and cost models on architecture and data placement for multimedia server have been proposed. However, these analytical techniques use only probabilistic models to represent the behavior of a system, and then they have several limitations like accuracy. Simulation is a viable alternative to analytical model. It avoids many of the limitations associated with analytical techniques, allowing for more precise representation of system attributes like workload in program code. In this paper, we propose a simulation test bed that can evaluate performance of real-time multimedia server by using simulation model.

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MediaCloud: A New Paradigm of Multimedia Computing

  • Hui, Wen;Lin, Chuang;Yang, Yang
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.6 no.4
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    • pp.1153-1170
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    • 2012
  • Multimedia computing has attracted considerable attention with the rapid growth in the development and application of multimedia technology. Current studies have attempted to support the increasing resource consumption and computational overhead caused by multimedia computing. In this paper, we propose $MediaCloud$, a new multimedia computing paradigm that integrates the concept of cloud computing in handling multimedia applications and services effectively and efficiently. $MediaCloud$ faces the following key challenges: heterogeneity, scalability, and multimedia Quality of Service (QoS) provisioning. To address the challenges above, first, a layered architecture of $MediaCloud$, which can provide scalable multimedia services, is presented. Then, $MediaCloud$ technologies by which users can access multimedia services from different terminals anytime and anywhere with QoS provisioning are introduced. Finally, $MediaCloud$ implementation and applications are presented, and media retrieval and delivery are adopted as case studies to demonstrate the feasibility of the proposed $MediaCloud$ design.

Study of Parallel Network Processor using Global Cache (글로벌 캐시를 이용한 네트워크 병렬 프로세서 구조 연구)

  • Park, Jae-Won;Chung, Won-Young;Kim, Hyun-Pil;Lee, Jung-Hee;Lee, Yong-Surk
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.1B
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    • pp.80-85
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    • 2011
  • The mount of network traffic from the Internet is increasing because of the use of Broadband Convergence Networks(BcN). Network traffic is also increasing because of the development of application, especially multimedia traffic from IPTV, VOD, and online games. This multimedia traffic not only has a huge payload but also should be considered a threat in real time. For this reason, this study examines the ways that routers distribute the bandwidth in accordance to traffic properties. To classify the property of the traffic, it is essential to analyze the application layer. However, the general network processor architecture serially processes the L2-4 and L7 layer. We propose a novel parallel network processor architecture with a global cache that processes L2-4 and L7 in parallel. To verify the proposed architecture, we simulated both of the architecture with SystemC. EEMBC and SNORT was used to measure L2-4 and L7 processing time. When multimedia traffic was entered into the network processor in the same flow, the proposed architecture showed about 85% higher performance than general architecture.

CLR Performance Improvement of Random Traffic in the Wireless ATM Access Architecture (무선 ATM 접속구조에서 랜덤 트래픽의 셀 손실율 성능개선)

  • 김철순;이하철;곽경섭
    • Journal of Korea Multimedia Society
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    • v.6 no.7
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    • pp.1239-1244
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    • 2003
  • In this paper, we analyzed cell loss rate performance for random traffic sources in wireless ATM(Asynchronous Transfer Mode) access architecture, which consists of access node and wireless channel. Applying queueing model to cell level at access node and considering burst error characteristics in wireless channel, we derived a formula about the cell loss rate of the random traffic in the wireless ATM access architecture. We also applied FEC(Forward Error Correction) schemes to improve the cell loss rate of random traffic. When we applied FEC schemes in the wireless ATM access architecture, we confirmed that the concatenated code provides the most superior performance compared to any other codes.

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A 4-way Pipelined Processing Architecture for Three-Step Search Block Matching Algorithm (3 단계 블록 매칭 알고리즘을 위한 4-경로 파이프라인 처리)

  • Jung, Sung-Tae;Lee, Sang-Seol;Nam, Kung-Moon
    • Journal of Korea Multimedia Society
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    • v.7 no.8
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    • pp.1170-1182
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    • 2004
  • A novel 4-way pipelined processing architecture is presented for three-step search block-matching motion estimation. For the 4-way pipelined processing, we have developed a method which divides the current block and search area into 4 subregions respectively and processes them concurrently. Also, we have developed memory partitioning method to access pixel data from 4 subregions concurrently without memory conflict. The architecture has been designed and simulated with C language and VHDL. Experimental results show that the proposed architecture achieves a high performance for real time motion estimation.

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