• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.2168-2180
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• 2014

In this paper, a generalized power loss algorithm for multilevel neutral-point clamped (NPC) PWM inverters is presented, which is applicable to any level number of multilevel inverters. In the case of three-level inverters, the conduction loss depends on the MI (modulation index) and the PF (power factor), and the switching loss depends on a switching frequency, turn-on and turn-off energy. However, in the higher level of inverters than the three-level, the loss of semiconductor devices cannot be analyzed by conventional methods. The modulation depth should be considered in addition, to find the different conducting devices depending on the MI. In a case study, the power loss analysis for the three- and five-level NPC inverters has been performed with the proposed algorithm. The validity of the proposed algorithm is verified by simulation for the three-and five-level NPC inverters and experiment for three-level NPC inverter.

• 전력전자학회논문지
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• 제20권5호
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• pp.448-455
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• 2015

A model predictive control (MPC) method without individual PWM has been recently researched to simplify and improve the control flexibility of a multilevel inverter. However, the input power of each H-bridge cell and the switching frequency of switching devices are unbalanced because of the use of a restricted switching state in the MPC method. This paper proposes a control method for balancing the switching patterns and cell power supplied from each isolated dc source of a cascaded H-bridge inverter. The supplied dc power from isolated dc sources of each H-bridge cells is balanced with the proposed cell balancing method. In addition, the switching frequency of each switching device of the CHB inverter becomes equal. A simulation and experimental results are presented with nine-level and five-level three-phase CHB inverter to validate the proposed balancing method.

• 전력전자학회논문지
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• 제15권4호
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• pp.288-295
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• 2010

멀티레벨 인버터는 대용량 전력변환 분야의 요구를 만족하면서 파형왜곡을 감소시켜 전력품질 향상시킬 수 있으므로 근래에 상당히 주목받고 있다. 그런데 전압레벨이 증가함에 따라 복잡한 PWM 알고리즘을 구현하는데 FPGA가 적합하다. 본 논문에서는 FPGA로 5-레벨 다이오드 클램핑형 멀티레벨 인버터의 PWM 신호발생 기법을 제시한다. 유도전동기 제어용 DSP와 FPGA사이에 3상 기준전압 값을 안정되게 전송하는 기법을 제시한다. 32-비트 DSP와 cyclone-III FPGA를 사용한 실험 및 시뮬레이션을 통하여 반송신호 발생 방법으로 PWM 신호를 발생시키는 기법의 타당성을 검증한다.

• Journal of Power Electronics
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• 제10권3호
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• pp.262-269
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• 2010

This paper proposes a practical design for a Cascaded H-Bridge Multilevel (CHBM) inverter based on Power Electronics Building Blocks (PEBB) and high performance control to improve current control and increase fault tolerance. It is shown that the expansion and modularization characteristics of the CHBM inverter are improved since the individual inverter modules operate more independently, when using the PEBB concept. It is also shown that the performance of current control can be improved with voltage delay compensation and the fault tolerance can be increased by using unbalance three-phase control. The proposed design and control methods are described in detail and the validity of the proposed system is verified experimentally in various industrial fields.

• 전력전자학회논문지
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• 제15권5호
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• pp.376-380
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• 2010

본 논문에서는 양방향 스위치를 가지는 기존의 5-레벨 인버터를 직렬 결합하여 다수의 출력 전압 레벨을 형성할 수 있는 멀티레벨 인버터 구조를 제안한다. 무엇보다도 제안된 회로의 입력 전압원 크기를 5의 배수로 구성함으로서 보다 많은 수의 레벨을 생성시킬 수 있다. 동일한 수의 출력 전압 레벨 형성시 기존의 Cascaded H-bridge cell 방식보다 스위칭 소자를 줄일 수 있어 시스템 크기, 비용, 전력 손실을 저감시킬 수 있는 장점을 가진다. 두 대의 5-레벨 인버터를 직렬 결합함으로써 25-레벨의 출력전압을 생성시킬 수 있는 인버터에 대한 특성을 분석하고 시뮬레이션과 실험을 통해 타당성을 검증한다.

• Journal of Electrical Engineering and Technology
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• 제12권2호
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• pp.701-710
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• 2017

This paper presents a five-level PWM inverter using series and parallel connection of voltage sources. The alternative connection is done by an auxiliary circuit consisted of a switch, three diodes, and two batteries. The auxiliary circuit is located between input dc voltage source and H-bridge cell. Thanks to the auxiliary circuit, the proposed inverter synthesizes five-level output voltage in an effective way. Topologically both batteries are charged and discharged in the same rate, so it does not need to apply battery voltage balancing control method. Theoretical analysis of the proposed inverter is verified by computer-aided simulation and experiment based on a prototype of 1kW.

• Journal of Power Electronics
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• 제12권2호
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• pp.285-293
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• 2012

Multilevel inverters have gained attention in high-power applications due to their numerous advantages in comparison with conventional two-level inverters. In this paper a simplified Space-Vector Modulation (SVM) algorithm for a three-level Neutral-Point Clamped (NPC) inverter is implemented on a Freescale$^{(R)}$ DSP56F8037. The algorithm is based on a simplification of the space-vector diagram for a three-level inverter so that it can be used with a two-level inverter. Once the simplification has been achieved, calculation of the dwell times and the switching sequences are carried out in the same way as for the two-level SVM method. Details of the hardware design are included. Experimental results are analyzed to validate the performance of the simplified algorithm.

• Journal of Electrical Engineering and Technology
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• 제9권2호
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• pp.489-500
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• 2014

This paper presents a simple modified unipolar carrier-based pulsewidth modulation (CB-PWM) strategy for the three-level neutral-point-clamped (NPC) voltage source inverter (VSI). Analytical expressions for the relationship between modulation reference signals and output voltages are derived. The proposed modulation technique for the three-level NPC VSI includes the maximum and minimum of the three-phase sinusoidal reference voltages with zero-sequence voltage injection concept. The proposed modified CB-PWM strategy incorporates a novel method that requires only of one triangular carrier wave for generate the gating pulses in three-level NPC VSI. It has the advantages of being simplifying the algorithm with no need of complex two/multi-carrier pulsewidth modulation or space vector modulation (SVM) and it's also simple to implement. The possibility of the proposed CB-PWM technique has been verified though computer simulation and experimental results.

• Journal of Power Electronics
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• 제10권4호
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• pp.374-381
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• 2010

Typical power electronic converters employ only pulse width modulation (PWM) to generate specific switching patterns. In this paper, a novel control strategy combining both pulse-width and amplitude modulation strategies (PWAM) has been proposed for power converters. The Pulse Amplitude Modulation (PAM), used in communication systems, has been applied to power electronic converters. This increases the degrees of freedom in eliminating or mitigating harmonics when compared to the conventional PWM strategies. The role of PAM in the novel PWAM strategy is based on the control of the converter's dc sources values. Software implementation of the conventional PWM and the PWAM control strategies has been applied to a five-level inverter for mitigating selective harmonics. Results show the superiority of the proposed strategy from the THD point of view along with a reduction in the inverter power dissipation.

• 전력전자학회논문지
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• 제8권6호
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• pp.478-487
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• 2003

본 논문에서는 고압 대용량 전동기 구동용 멀티레벨 인버터의 종류 및 특징을 간략히 살펴보고, 특히 입출력 전력품질이 우수하고 전압별 시리즈화가 용이한 H-브릿지 멀티레벨 인버터의 구조적 특징 및 장점을 기술하였다. 연구 개발된 3,300V lMVA 용량의 Cascaded H-브릿지 멀티레벨 인버터의 구체적인 전력회로 구조 및 설계방법, 제어기 구성 그리고 PWM 기법을 제시하였다. 또한, 실용량의 시험을 통해 H-브릿지 멀티레벨 인버터는 출력 전압 Step이 여러 단계이고 dv/dt가 적으며 입력단 THD를 크게 낮출 수 있어 성능 면에서도 여타 방식보다 우수함을 입증하였다. 또한 생산적인 측면에서도 저압 소자를 사용하여 설계하므로 기존의 생산/시험 기술과 설비를 이용할 수 있어 매우 경제적이며 Power Cell 단위 결합 구조이므로 신뢰성 측면이나 보수/유지 측면에서도 유리하다는 결론을 얻었다.