• Journal of Magnetics
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• v.16 no.3
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• pp.234-239
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• 2011

Transcranial magnetic stimulation utilizes the method of controlling applied time and changing pulse by output pulse through power density control for diagnosis purposes. Transcranial magnetic stimulation can also be used in cases where diagnosis and treatment are difficult since output pulse shape can be changed. As intensity, pulse range, and pulse shape of the stimulation pulse must be changed according to lesion, the existing sine wave-shaped stimulation treatment pulse poses limitations in achieving various treatments and diagnosis. This study actualized a new method of transcranial magnetic stimulation that applies a 3 Stage 2 Switch( power semiconductor 2EA) for controlling pulse repetition rate by achieving numerous switching control of stimulation coil. Intensity, pulse range, and pulse shape of output can be freely changed to transform various treatment pulses in order to overcome limitations in stimulation treatment presented by the previous sine wave pulse shape. The method of freely changing pulse range by using 3 Stage 2 Switch discharge method is proposed. Pulse shape, composed of various pulse ranges, was created by grafting PFN (Pulsed Forming Network) through AVR AT80S8535 one-chip microprocessor technology, and application in transcranial magnetic stimulation was achieved to study the output characteristics of stimulation treatment pulse according to delaying time of the trigger signal applied in section switch.

• Journal of Institute of Control, Robotics and Systems
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• v.12 no.12
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• pp.1241-1248
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• 2006

In high reliability systems for industrial network such as railway signal system, fieldbus protocols have been known to satisfy the real-time and fault tolerant requirements. But, the application of fieldbus has been limited due to the high cost of hardware and software, and the difficulty in interfacing with multi-vendor products. Therefore, as an alternative to fieldbus, the computer network technology, especially Ethernet(IEEE 802.3), is being adapted to the industrial network. In this paper, we propose a switched Ethernet based railway signal system because of its very promising prospect for industrial application due to the elimination of uncertainties in the network operation. In addition, we propose the redundancy architecture for the reliability of network components. More specifically, this paper presents an analytical performance evaluation of switched Ethernet for railway signal system, and shows experimental evaluation of redundancy architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.937-944
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• 2002

The current fast-growing Internet traffic is demanding more and more network capacity. Photonic packet switching offers high-speed, data rate/format transparency, and configurability, which are some of the important characteristics needed in future networks supporting different forms of data. In this paper, we define that optical backbone networks for IP transport consist of optical packet core switches and optical fibers. We propose a multi-link photonic packet switch managing as single media which unifies the whole bandwidth of multiple wavelengths on the optical fiber in the WDM optical networks. The proposed switch uses optical packet memories of output link equally as well as using the WDM buffer. So it cuts down the required number of buffers and realizes of the optical packet memory economically.

• Journal of Communications and Networks
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• v.6 no.1
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• pp.60-67
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• 2004

With the fast growth of Internet and a new widespread interest in optical networks, the unparalleled potential of Multi-Protocol Label Switching (MPLS) is leading to further research and development efforts. One of those areas of research is Path Protection Mechanism. It is widely accepted that layer three protection and recovery mechanisms are too slow for today’s reliability requirements. Failure recovery latencies ranging from several seconds to minutes, for layer three routing protocols, have been widely reported. For this reason, a recovery mechanism at the MPLS layer capable of recovering from failed paths in 10’s of milliseconds has been sought. In light of this, several MPLS based protection mechanisms have been proposed, such as end-to-end path protection and local repair mechanism. Those mechanisms are designed for intra-domain recoveries and little or no attention has been given to the case of non-homogenous independent inter-domains. This paper presents a novel solution for the setup and maintenance of independent protection mechanisms within individual domains and merged at the domain boundaries. This innovative solution offers significant advantages including fast recovery across multiple nonhomogeneous domains and high scalability. Detailed setup and operation procedures are described. Finally, simulation results using OPNET are presented showing recovery times of a few milliseconds.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.687-688
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• 2011

This paper presents a design method for combinational digital logic systems using time domain based multiplexing(TDBM) and common multi-terminal extension decision diagrams(CMTEDD). The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams(DDs), that is the common binary decision diagrams(CBDDs) and CMTEDDs. Also, we propose an algorithms to derive common multiple-terminal binary decision diagrams(CMTBDD) from CBDDs, and CMTEDDs from CMTBDDs. The CMTEDDs over CBDDs is more compactness in terms of number of non-terminal nodes, where the nodes for output selection variables are not included in the non-terminal nodes. In the logic design, each non-terminal nodes of an CBDDs and an CMTEDDs is realized by a multiplexer(MUX). In addition, we compare the proposed TDBM realization with the conventional one.

• Journal of Power Electronics
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• v.15 no.4
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• pp.899-909
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• 2015

A dual-input boost-buck converter with coupled inductors (DIBBC-CI) is proposed as a thermoelectric generator (TEG) power conditioner with a wide input voltage range. The DIBBC-CI is built by cascading two boost cells and a buck cell with shared inverse coupled filter inductors. Low current ripple on both sides of the TEG and the battery are achieved. Reduced size and power losses of the filter inductors are benefited from the DC magnetic flux cancellation in the inductor core, leading to high efficiency and high power density. The operational principle, impact of coupled inductors, and design considerations for the proposed converter are analyzed in detail. Distributed maximum power point tracking, battery charging, and output control are implemented using a competitive logic to ensure seamless switching among operational modes. Both the simulation and experimental results verify the feasibility of the proposed topology and control.

• Journal of Power Electronics
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• v.15 no.2
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• pp.309-318
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• 2015

This study proposes a dual-output single-stage bridgeless single-ended primary-inductor converter (DOSSBS) that can completely remove the front-end full-bridge alternating current-direct current rectifier to accomplish power factor correction for universal line input. Without the need for bridge diodes, the proposed converter has the advantages of low component count and simple structure, and can thus significantly reduce power loss. DOSSBS has two uncommon output ports to provide different voltage levels to loads, instead of using two separate power factor correctors or multi-stage configurations in a single stage. Therefore, this proposed converter is cost-effective and compact. A magnetically coupled inductor is introduced in DOSSBS to replace two separate inductors to decrease volume and cost. Energy stored in the leakage inductance of the coupled inductor can be completely recycled. In each line cycle, the two active switches in DOSSBS are operated in either high-frequency pulse-width modulation pattern or low-frequency rectifying mode for switching loss reduction. A prototype for dealing with an $85-265V_{rms}$ universal line is designed, analyzed, and built. Practical measurements demonstrate the feasibility and functionality of the proposed converter.

• Proceedings of the Korea Information Processing Society Conference
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• 2000.04a
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• pp.686-691
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• 2000

최근 들어 인터넷의 사용이 급격히 증가함에 따라 인터넷의 백본망에는 패킷 전달의 고속성, 확장성 뿐만 아니라 QOS 보장을 요구하게 되었다. 효과적인 인터넷 백본망을 구현하기 위해 본 논문에서는 Multi-Protocol Label Switching(MPLS)를 고려하고 MPLS 에서 인터넷 Quality Of Service(QOS) 서비스 모델 중 백본망에 적합한 Differentiated Service(DS) 모델을 그대로 제공하기 위해 MPLS 와 DS 의 연동에 대한 문제를 다룬다. 우선 MPLS 에서 QOS 제공을 위한 기능요소를 정성적으로 분석한다. 그리고 두 DS 망 가운데 ATM 기반의 MPLS 망을 두고 있는 경우를 가정하여, 종단대 종단간 DS 제공을 위하여 DS 망과 MPLS 망에서의 시그널링 과정을 제안한다. 즉, DS 의 BB 로부터 SLA 를 위한 신호를 MPLS 의 입구 라우터에서 해석하여 DS Type-Length-Value(TLV)를 만들고 이를 이용하여 Constraint-based Label Distribution Protocol(CR-LDP) 시그널링을 통해 마다 Label-Only-Inferred-PSC LSP(L-LSP)를 설립하여 MPLS 에서 DS QOS 를 그대로 제공한다. 또한 입구 DS BB 로부터의 정보를 MPLS 망을 통해 BB 에게 보낸다.

• Journal of the Korea Society of Computer and Information
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• v.11 no.3
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• pp.161-166
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• 2006

In this paper, CPLD low power technology mapping using reuse module selection under the time constraint is proposed. Traditional high-level synthesis do not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed algorithm is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource Also, we are obtainable the optimal the scheduling result in experimental results of our using chaining and multi-cycling in the scheduling techniques. Low power circuit make using CPLD technology mapping algorithm for selection reuse module by scheduling.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.391-394
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• 2014

In this paper, we introduce a method of determining the absolute position of the rotor for the vector control of Hall sensor type multi-pole BLDC motor using the DSP(TMS320F28335), and implement an algorithm to complement the problems of the conventional method. The switching method of the inverter for providing desired sinusoidal current to each phase of a motor, we adopt Space-Vector pulse width modulation method. In order to increase the speed range, Field-Weakness control method are used. In order to verify the proposed algorithm, we compare the value of Iqe, Ide and phase currents with the values before compensated.