• Journal of Electrical Engineering and Technology
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• v.12 no.5
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• pp.1872-1882
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• 2017

Medium voltage drive systems driven by high-power multi-level inverters operating at low switching frequency can reduce the switching losses of the power device and increase the output power. Employing subsection synchronous current harmonic minimum pulse width modulation (CHMPWM) technique can maintain the total harmonic distortion of current at a very low level. It can also reduce the losses of the system, improve the system control performance and increase the efficiency of DC-link voltage accordingly. This paper proposes a subsection synchronous CHMPWM approach of active neutral point clamped five-level (ANPC-5L) inverter under low switching frequency operation. The subsection synchronous scheme is obtained by theoretical calculation based on the allowed maximum switching frequency. The genetic algorithm (GA) is adopted to get the high-precision initial values. So the expected switching angles can be achieved with the help of sequential quadratic programming (SQP) algorithm. The selection principle of multiple sets of the switching angles is also presented. Finally, the validity of the theoretical analysis and the superiority of the CHMPWM are verified through both the simulation results and experimental results.

• Journal of Electrical Engineering and Technology
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• v.10 no.3
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• pp.1066-1074
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• 2015

This paper presents the reverse recovery characteristic according to the change of switching states when Si diode and SiC diode are used as clamp diode and proposes a method to minimize the switching loss containing the reverse recovery loss in the neutral-point-clamped inverter at low modulation index. The previous papers introduce many multiple circuits replacing Si diode with SiC diode to reduce the switching loss. In the neutral-point-clamped inverter, the switching loss can be also reduced by replacing device in the clamp diode. However, the switching loss in IGBT is large and the reduced switching loss cannot be still neglected. It is expected that the reverse recovery effect can be infrequent and the switching loss can be considerably reduced by the proposed method. Therefore, it is also possible to operate the inverter at the higher frequency with the better system efficiency and reduce the volume, weight and cost of filters and heatsink. The effectiveness of the proposed method is verified by numerical analysis and experiment results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.12B
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• pp.1586-1594
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• 2011

LED-ID (light emitting diode - identification) technology is the new paradigm in the identification technology environment. LED-ID system typically needs line of sight (LOS) that supports narrow FOV transceivers links to achieve high data rate. On the other hand, narrow FOV reduces the coverage area. Therefore, the number of tags is increased significantly to cover the whole area. In this case number of link switching is increased when the reader moves within whole coverage area. Link switching delay is the important factor for the moving reader to maintain the communication with high data rate and better QoS. In this paper we propose in literature a new link switching scheme and measure the link switching delay time for LED-ID system. The simulation results show that the proposed link switching scheme is a possible candidate for multi-tag LED-ID system.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.10
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• pp.95-102
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• 2003

The buffering is a promising solution to resolve the contention problem in optical network. we study the packet loss probability and the dimensioning of optical buffer using a Fiber Delay Line for variable length packet. In this paper, we study the relation between the granularity and the loss of FDL buffer in Single-Stage FDL buffer and propose the Single-Bundle Multi-Stage FDL buffer. The Multi-Stage FDL buffer is too early yet to apply to the current backbone network, considering the current technology in view of costs. but we assume that the above restriction will be resolved in these days. The appropriate number of delay and pass line for a dimensioning is based on a amount of occupied time by packets. Once more another multi-stage FDL buffer is proposed, Split-Bundle multi-stage FDL buffer. The Split-Bundle ms-FDL buffer is more feasible for a FDL buffer structure, considering not only a size of switching matrix but also a bulk of switching element. its feasibility will be demonstrated from a loss probability.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.4
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• pp.71-78
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• 2005

This paper proposes a novel multi-level energy recovery sustaining driver for AC PDP(Plasma Display Panel), which solves the problems of the conventional multi-level sustaining driver. While the conventional circuit improves the voltage md current stress of the switching elements in Weber circuit not only there are parasitic resonant currents between resonant inductors and parasitic capacitance and hard switching, but also the changing period between 0 and sustain voltage is too long. Comparing the proposed circuit with the conventional circuit, the number of components are reduced and the parasitic resonant currents in resonant inductors are eliminated Moreover the hard switching problem is solved by using CIM(Current Injection Method) and the operating frequency will be high as much as possible by removing Vs/2 sustain period. And the circuit operations of the proposed circuit are analyzed for each mode and the validity is verified by the simulations using PSpice program.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.2
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• pp.194-202
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• 2005

This paper proposes a new multi-level energy recovery sustaining driver for AC PDP(Plasma Display Panel), which solves the problems and maintains the merits of the conventional multi-level sustaining driver. While the conventional circuit improves the hard switching in the Weber circuit, there exist parasitic resonant currents in resonant inductors and Vs/2 sustaining period. Comparing the proposed circuit with the conventional circuit, the number of inductors are reduced by half, the parasitic resonant currents in resonant inductors are eliminated, and the hard switching problem is solved by CIM(Current Injection Method). Moreover the voltages across series-connected switching elements in the full bridge circuit are distributed equally by adopting NPC(Neutral Point Clamping) techniques. And circuit operations of the proposed circuit are analyzed for each mode and the validity is verified by the simulations using PSpice program and experimentation with a prototype drive circuit.

• IEIE Transactions on Smart Processing and Computing
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• v.6 no.3
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• pp.220-227
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• 2017

Technology development is leading to the invention of more sophisticated electronics appliances that require long battery life. Therefore, saving power is a major concern in current-day scenarios. A notable source of power dissipation in sequential structures of integrated circuits is due to the continuous switching of high-frequency clock signals, which do not carry any information, and hence, their switching is eliminated by a method called clock gating. In this paper, we have incorporated a recent clock-gating style named Leakage Control Transistor (LECTOR)-based clock gating to drive a multi-stage sequential architectures, and we focus on its performance under three different process corners (fast-fast, slow-slow, typical-typical) through Monte Carlo simulation at 18 GHz clock with 90 nm technology. This gating is found to be one of the best gated approaches for multi-stage architectures in terms of total power consumption.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.4
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• pp.651-669
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• 2013

In this paper, we study a novel routing algorithm based on load balancing for multi-channel wireless mesh networks. In order to increase the network capacity and reduce the interference of transmission streams and the communication delay, on the basis of weighted cumulative expected transmission time (WCETT) routing metric this paper proposes an improved routing metric based on load balancing and channel interference (LBI_WCETT), which considers the channel interference, channel diversity, link load and the latency brought by channel switching. Meanwhile, in order to utilize the multi-channel strategy efficiently in wireless mesh networks, a new channel allocation algorithm is proposed. This channel allocation algorithm utilizes the conflict graph model and considers the initial link load estimation and the potential interference of the link to assign a channel for each link in the wireless mesh network. It also utilizes the channel utilization percentage of the virtual link in its interference range as the channel selection standard. Simulation results show that the LBI_WCETT routing metric can help increase the network capacity effectively, reduce the average end to end delay, and improve the network performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.504-510
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• 2015

This paper presents a power and area efficient SAR ADC for multi-channel near threshold-voltage (NTV) applications such as neural recording systems. This work proposes a split dual-capacitive-array (S-DCA) structure with shifted input range for ultra low-switching energy and architecture of multi-channel single-ended SAR ADC which employs only one comparator. In addition, the proposed ADC has the same amount of equivalent capacitance at two comparator inputs, which minimizes the kickback noise. Compared with conventional SAR ADC, this work reduces the total capacitance and switching energy by 84.8% and 91.3%, respectively.

• Journal of Power Electronics
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• v.16 no.2
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• pp.610-620
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• 2016

The compound active clamp zero voltage soft switching (CACZVS) three-phase power factor correction (PFC) converter has many advantages, such as high efficiency, high power factor, bi-directional energy flow, and soft switching of all the switches. Triple closed-loop PI controllers are used for the three-phase power factor correction converter. The control objectives of the converter include a fast transient response, high accuracy, and unity power factor. There are six parameters of the controllers that need to be tuned in order to obtain multi-objective optimization. However, six of the parameters are mutually dependent for the objectives. This is beyond the scope of the traditional experience based PI parameters tuning method. In this paper, an improved chaotic particle swarm optimization (CPSO) method has been proposed to optimize the controller parameters. In the proposed method, multi-dimensional chaotic sequences generated by spatiotemporal chaos map are used as initial particles to get a better initial distribution and to avoid local minimums. Pareto optimal solutions are also used to avoid the weight selection difficulty of the multi-objectives. Simulation and experiment results show the effectiveness and superiority of the proposed method.