IEIE Transactions on Smart Processing and Computing

The Institute of Electronics and Information Engineers (대한전자공학회)
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A 23.52µW / 0.7V Multi-stage Flip-flop Architecture Steered by a LECTOR-based Gated Clock

  • Bhattacharjee, Pritam (VLSI Design Laboratory, Department of Electronics & Computer Engineering, National Institute of Technology) ;
  • Majumder, Alak (VLSI Design Laboratory, Department of Electronics & Computer Engineering, National Institute of Technology) ;
  • Nath, Bipasha (VLSI Design Laboratory, Department of Electronics & Computer Engineering, National Institute of Technology)
  • Received : 2017.02.08
  • Accepted : 2017.04.12
  • Published : 2017.06.30
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Abstract

Technology development is leading to the invention of more sophisticated electronics appliances that require long battery life. Therefore, saving power is a major concern in current-day scenarios. A notable source of power dissipation in sequential structures of integrated circuits is due to the continuous switching of high-frequency clock signals, which do not carry any information, and hence, their switching is eliminated by a method called clock gating. In this paper, we have incorporated a recent clock-gating style named Leakage Control Transistor (LECTOR)-based clock gating to drive a multi-stage sequential architectures, and we focus on its performance under three different process corners (fast-fast, slow-slow, typical-typical) through Monte Carlo simulation at 18 GHz clock with 90 nm technology. This gating is found to be one of the best gated approaches for multi-stage architectures in terms of total power consumption.

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References

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