• Journal of Korea Society of Digital Industry and Information Management
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• v.11 no.1
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• pp.27-35
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• 2015

Increasing the number of GPU (Graphic Processor Unit) cores, the studies on High Performance Computing Platform using GPU have actively been made in recent. This trend has led to the development of GPGPU (General Purpose GPU) and CUDA (Compute Unified Device Architecture) Framework. In this paper, we explain the many benefits of the GPU based system, and propose the ICIDF(Identify Compute-Intensive Data set and Function) methodology to apply GPU technology to legacy military information system for performance improvement. To demonstrate the efficiency of this methodology, we applied this method to AES CPU based program obtained from the Internet web site. Simply changing the data structure made improved the performance of AES program. As a result, the performance of AES based GPU program is improved gradually up to 10 times. Depending on the developer's ability, additional performance improvement can be expected. The problem to be solved is heat issue, but this problem has been much improved by the development of the cooling technology.

• Journal of Computing Science and Engineering
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• v.6 no.1
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• pp.12-25
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• 2012

For real-time systems it is important to obtain the accurate worst-case execution time (WCET). Furthermore, how to improve the WCET of applications that run on multicore processors is both significant and challenging as the WCET can be largely affected by the possible inter-core interferences in shared resources such as the shared L2 cache. In order to solve this problem, we propose an innovative approach that adopts a code positioning method to reduce the inter-core L2 cache interferences between the different real-time threads that adaptively run in a multi-core processor by using different strategies. The worst-case-oriented strategy is designed to decrease the worst-case WCET among these threads to as low as possible. The other two strategies aim at reducing the WCET of each thread to almost equal percentage or amount. Our experiments indicate that the proposed multicore-aware code positioning approaches, not only improve the worst-case performance of the real-time threads but also make good tradeoffs between efficiency and fairness for threads that run on multicore platforms.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.7
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• pp.354-360
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• 2008

Power-related issues have become important considerations in current generation microprocessor design. One of these issues is that of elevated on-chip temperatures. This has an adverse effect on cooling cost and, if not addressed suitably, on chip reliability. In this paper we investigate the general trade-offs between temporal and spatial hot spot mitigation schemes and thermal time constants, workload variations and microprocessor power distributions. By leveraging spatial and temporal heat slacks, our schemes enable lowering of on-chip unit temperatures by changing the workload in a timely manner with Operating System (OS) and existing hardware support.

• Journal of Astronomy and Space Sciences
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• v.13 no.2
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• pp.163-172
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• 1996

The objective of this paper is to show how digital signal processing experiment(DSPE) was designed and to present its experimental results in orbit and on the ground. The multi-missional and flexible DSPE was designed in a reliable manner. Among several experiments executed in orbit and on the ground, a high-speed(19.2kbps) software modulator experiment was discussed in this paper. A 32bit floating-type TMS320C30, which was developed for commercial purposes, was used on LEO micro-satellites, KITSAT-1 and KITSAT-2. This digital signal processor(DSP) can be applied to the various payloads of the next generation satellites.

• Aerospace Engineering and Technology
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• v.3 no.1
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• pp.109-116
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• 2004

In a satellite time management system, the GPS-based clock synchronization technique[1] has the merits of precision time management by knowing the time difference or the error between the OBT(On Board Time) of the internal processors and GPS time every second. It can be realized employing the DPLL(Digital Phase Loop Lock) and FEP(Front End Processor) circuitry for the clock synchronization[2]. In this paper, a refined DPLL & FEP scheme is proposed to provide the precision, stability and robustness of the operation, which is to compensate the errors and noise of the GPS signal, and also to cope with the case when the GPS signal is lost due to several reasons. The simulation and HIL (Hardware In the Loop) test results using the FM(Flight Model) in the course of KOMPSAT-2(Korea Multi Purpose Satellite-2) design and development are illustrated to demonstrate the salient features of this methodology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11B
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• pp.1659-1666
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• 2010

The High maneuver missiles use various interfaces and high speed guidance and control loop. Hardware-in-the-Loop(HWIL) simulation control system, therefore, should have high performance computing power and hardware interface capabilities, and should be developed using IT technology with which real time operating system, embedded system, data communication technology, and real time hardware control are integrated. This paper suggests the control system design techniques, such as a system hardware configuration, a job distribution algorithm for high performance multi-processors, a real time calculation and control mechanism, inter-processor communication mechanism, and a real time data acquisition technique, to perform the HWIL simulation for high maneuver missile system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11B
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• pp.1631-1639
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• 2010

This paper proposes a scheduling algorithm that can reduce the power consumed for execution of application programs and the communication cost incurred due to dependencies among tasks. The proposed scheduling algorithm can increase energy efficiency of the DVS(Dynamic Voltage Scaling) by estimating laxity usage during scheduling, making up for conventional algorithms that apply the DVS after scheduling. Energy efficiency can be increased by applying the proposed algorithm to complex multimedia applications. Experimental results show that energy consumptions for executing HD MPEG4, MotionJPEG codec, MP3, and Wavelet have been reduced by 11.2% on the average, when compared to conventional algorithms.

• KIEE International Transactions on Power Engineering
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• v.4A no.3
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• pp.129-133
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• 2004

This paper deals with the design and implementation of a TCSC (Thyristor Controlled Series Capacitor) simulator, which is a module for an analog type power system simulator. Principally, it presents configuration of controller hardware/software and its experimental results. An analog type power system simulator consists of numerous power system components, such as various types of generator models, scale-downed transmission line modules, transformer models, switches and FACTS (Flexible AC Transmission System) devices. It has been utilized for the verification of the control algorithm and the study of system characteristics analysis. This TCSC simulator is designed for 50% line compensation rate and considered for damping resister characteristic analysis. Its power rate is three phase 380V 20kVA. For hardware extendibility, its controller is designed with VMEBUS and its main CPU is TMS320C32 DSP (Digital Signal Processor). For real time control and communications, its controller is applied to the RTOS (Real Time Operation System) for multi-tasking. This RTOS is uC/OS-II. The experimental results of capacitive mode and inductive mode operations verify the fundamental operations of the TCSC.

• Journal of the Korean Society of Marine Environment & Safety
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• v.1 no.2
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• pp.69-82
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• 1995

This study is concerned with developing a heuristic algorithm for solving a class of ninlinear integer programs(NLIP). Exact algrithm for solving a NLIP either may not exist, or may take an unrealistically large amount of computing time. This study develops a new heuristic, the Excursion Algorithm(EA), for solving a class of NLIP's. It turns out that excursions over a bounded feasible and/or infeasible region is effective in alleviation the risks of being trapped at a lical optimum. The developed EA is applied to the redundancy optimization problems for improving the system safety, and is compared with other existing heuristic methods. We also include simulated annealing(SA) method in the comparision experiment due to ist populatrity for solving complex combinatorial problems. Computational results indicate that the proposed EA performs consistently better than the other in terms of solution quality, with moderate increase in computing time. Therefore, the proposed EA is believed to be an attractive alternative to other heuristic methods.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.9
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• pp.113-119
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• 2005

The methods that are used for receiving data from attached devices under real-time preemptive multi-task operating system (OS) by general processors can be categorized as polling and interrupt driven. The technical approach to these methods may be different due to the application specific scheduling policy of the OS and the programming architecture of the flight software. It is one of the most important requirements on the development of the flight software to process the data received from satellite subsystems or components with the exact timeliness and accuracy. This paper presents the analysis of the I/O method of device related scheduling mechanism and the reliable data I/O methods between processor and devices.