• Journal of the Korean Institute of Intelligent Systems
• /
• v.12 no.2
• /
• pp.135-143
• /
• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast courier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like {0, 1, 2, 3}. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used toed as LUT(Lood Up Table).

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.11A
• /
• pp.1271-1277
• /
• 2004

We propose a foe phase tuner and a rounding processor for a numerically controlled oscillator (NCO), yielding a reduced phase error in generating a digital sine waveform. By using the fine Phase tuner Presented in this paper, when the ratio of the desired sine wave frequency to the clock frequency is expressed as a fraction, an accurate adjustment in representing the fractional value can be achieved with simple hardware. In addition, the proposed rounding processor reduces the effects of phase truncation on the output spectrum. Logic simulation results of the NCO for multi-carrier channel separation in cdma2000 3X multi-carrier receive system using these techniques show that the noise spectrum and mean square error (MSE) are reduced by 8.68 dB and 5.5 dB, respectively compared to those of truncation method and 2.38 dB and 0.83 dB, respectively, compared to those of Paul's scheme.

• The KIPS Transactions:PartA
• /
• v.9A no.2
• /
• pp.147-162
• /
• 2002

Multi-processor system with fast I/O devices improves processing performance and reduces the bottleneck by I/O concentration. In the system, the Performance influenced by shared memory used for exchanging data between processors varies with configuration and utilization. This paper suggests a prediction model for buffer and shared memory optimization under interrupt recognition method using mailbox. Ethernet (IEEE 802.3) packets are used as the input of system and the amount of utilized memory is measured for different network bandwidth and burstiness. Some empirical studies show that the amount of buffer and shared memory varies with packet concentration rate as well as I/O bandwidth. And the studies also show the correlation between two memories.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2019.05a
• /
• pp.133-136
• /
• 2019

Recently, many industrial devices are facing protocol compatibility problems with external monitoring and control systems. This paper designed an industrial communication gateway that can support the transformation of industrial communication protocol using multi-layered communication module. Industrial communication gateways have a structure that connects individual communication modules using rs485 serial communication to multiple layers. Each communication module consisted of analog data card, a digital data card LAN, and a CAN-enabled card. The main board processor used Atmega micro-processor, and the rs485 serial slot was placed to have a multi-layer communication module structure. These additive layer type communication modules support analog and digital I/O functions and LAN and CAN for wide use in industrial communication control and monitoring.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.4
• /
• pp.885-892
• /
• 2013

In the model Utilizing the TCP / IP socket communication to transmit and receive data, if the size of data is small and if data-transmission aren't frequently requested, the importance of communication speed between a server and a client isn't emphasized. But nowadays, it has emerged for large amounts of data transfer requests and frequent data transfer request. This paper propose the TCP/IP communication model that can be improved the data transfer rate in multi-core environment by changing the receiving structure of the client to receive large amounts of data and the transmission structure of the server to send large amounts of data.

• KIEE International Transactions on Power Engineering
• /
• v.5A no.3
• /
• pp.214-220
• /
• 2005

In order to improve energy efficiency and solve power disturbances, power components measurement for both the supply and demand side of a power system must be implemented before appropriate action on the power problems can be taken. This paper presents a DSP (Digital Signal Processor)-based multi-channel (voltage 8-channel and current 10-channel) power measurement system that can simultaneously measure and analyze power components for both supply and demand. Voltage 8-channel and current 10-channel measurement is made through voltage and current sensors connected to the developed system, and power components such as reactive power, power factor and harmonics are calculated and measured by the DSP. The measured data are stored in a personal computer (PC) and a commercial program is then used for measurement data analysis and display. After voltage and current measurement accuracy revision using YOKOGAWA 2558, the developed system was tested using a programmable ac power source. The test results showed the accuracy of the developed system to be about 0.3 percent. Also, a simultaneous measurement field test of the developed system was implemented by application to the supply and demand side of the three-phase power system.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.7
• /
• pp.52-60
• /
• 2010

In this paper, we propose a dynamic power management framework for multi-core systems. We reduced the power consumption of multi-core processors such as Intel Centrino Duo and ARM11 MPCore, which have been used at the consumer electronics and personal computer market. Each processor uses a different technique to save its power usage, but there is no embedded multi-core processor which has a precise power control mechanism such as dynamic voltage scaling technique. The proposed dynamic power management framework is suitable for smart phones which have an operating system to provide multi-processing capability. Basically, our framework follows an intuitive idea that reducing the power consumption of idle cores is the most effective way to save the overall power consumption of a multi-core processor. We could minimize the energy consumption used by idle cores with application-targeted policies that reflect the characteristics of active workloads. We defined some properties of an application to analyze the performance requirement in real time and automated the management process to verify the result quickly. We tested the proposed framework with popular processors such as Intel Centrino Duo and ARM11 MPCore, and were able to find that our framework dynamically reduced the power consumption of multi-core processors and satisfied the performance requirement of each program.

• ETRI Journal
• /
• v.22 no.4
• /
• pp.13-24
• /
• 2000

As more transistors are integrated onto bigger die, an on-chip multiprocessor will become a promising alternative to the superscalar microprocessor that dominates today's microprocessor marketplace. This paper describes key parts of a new on-chip multiprocessor, called Raptor, which is composed of four 2-way superscalar processor cores and one graphic co-processor. To obtain performance characteristics of Raptor, a program-driven simulator and its programming environment were developed. The simulation results showed that Raptor can exploit thread level parallelism effectively and offer a promising architecture for future on-chip multi-processor designs.

• Journal of Institute of Control, Robotics and Systems
• /
• v.6 no.6
• /
• pp.492-499
• /
• 2000

In this paper, realization techniques of the parallel processing and the parallel network system for image processing are described. The parallel image processing system is constructed by the characterization of image processing and processor. Several problems are solved to achieve effective parallel processing and processor networking with the particular properties of image processing, which are reduction of communication quantity, equalization of load and delay depreciation on communication. A parallel image input device is developed for the flexible networking of parallel image processing. An abnormal region detection algorithm which is the basic function in machine vision is applied to evaluate the constructed parallel image processing system. The performance and effectiveness of the system are confirmed by experiments.

• Journal of Information Processing Systems
• /
• v.7 no.3
• /
• pp.435-446
• /
• 2011

Microprocessors are becoming increasingly vulnerable to soft errors due to the current trends of semiconductor technology scaling. Traditional redundant multi-threading architectures provide perfect fault tolerance by re-executing all the computations. However, such a full re-execution technique significantly increases the verification workload on the processor resources, resulting in severe performance degradation. This paper presents a pro-active verification management approach to mitigate the verification workload to increase its performance with a minimal effect on overall reliability. An anomaly-speculation-based filter checker is proposed to guide a verification priority before the re-execution process starts. This technique is accomplished by exploiting a value similarity property, which is defined by a frequent occurrence of partially identical values. Based on the biased distribution of similarity distance measure, this paper investigates further application to exploit similar values for soft error tolerance with anomaly speculation. Extensive measurements prove that the majority of instructions produce values, which are different from the previous result value, only in a few bits. Experimental results show that the proposed scheme accelerates the processor to be 180% faster than traditional fully-fault-tolerant processor with a minimal impact on overall soft error rate.