• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.129-131
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• 2004

Elliptic Curve Cryptography (ECC) coprocessors support massive scalar multiplications of a point. We research the design for multi-segment multipliers in fixed-size ECC coprocessors using the multi-segment Karatsuba algorithm on GF($2^m$). ECC coprocessors of the proposed multiplier is verified on the SoC-design verification kit which embeds ALTERA EXCALIBUR FPGAs. As a result of our experiment, the multi-segment Karatsuba multiplier, which has more efficient performance about twice times than the traditional multi-segment multiplier, can be implemented as adding few H/W resources. Therefore the multi-segment Karatsuba multiplier which satisfies performance for the cryptographic algorithm, is adequate for a low cost embedded system, and is implemented in the minimum area.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.719-727
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• 2016

This paper proposes a unified medium access control (MAC) design methodology and presents the implementation of the IEEE 802.11ac down-link multi-user multi-input and multi-output wireless local area network MAC using the proposed design methodology. The proposed methodology employs unified code for both network simulation and system implementation. Because the unified code closely relates these two processes, the performance of the implemented MAC system can be estimated before implementation. The MAC architecture for an access point implemented using the proposed design methodology is verified on an ARM-based platform, and it is applied to a 65 nm CMOS library.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.12
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• pp.2140-2145
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• 2008

We design and synthesize a 128-point FFT processor for multi-band OFDM, which can be applied to a UWB transceiver. The structure of a 128-point FFT processor is based on a Radix-2 FFT algorithm and a R2SDF pipeline architecture. The algorithm is efficiently modeled in VHDL and the result is simulated using Modelsim. Finally, they are synthesized on Xilinx Vertex-II FPGA, and an operational frequency of 18.7MHz has been obtained. It is expected that the proposed 128-point FFT processor can be applied to an entire FFT block as one of parallel processed FFTs. In order to obtain the enhanced maximum frequency of operation, we design the FFT module consisting of four 128-point FFT processors for parallel process. As a result, we achieve the performance requirement of computing the FFT module in multi-band OFDM symbol timing in 90nm ASIC process.

• Advances in aircraft and spacecraft science
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• v.10 no.3
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• pp.245-256
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• 2023

In order to improve aerodynamic performance of multi-stage axial flow turbines used in aircraft engines, a one-dimensional aerodynamic design and optimization framework is constructed. In the method, flow path is generated by solving mass continuation and energy conservation with loss computed by the Craig & Cox model; Also real gas properties has been taken into consideration. To obtain an optimal result, a multi-objective genetic algorithm is used to optimize the efficiencies and determine values of various design variables; Final design can be selected from obtained Pareto optimal solution sets. A three-stage axial turbine is used to verify the effectiveness of the developed optimization framework, and designs are checked by three-dimensional CFD simulation. Results show that the aerodynamic performance of the optimized turbine has been significantly improved at design point, with the total-to-total efficiency increased by 1.17% and the total-to-static efficiency increased by 1.48%. As for the off-design performance, the optimized one is improved at all working points except those at small mass flow.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.2
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• pp.432-438
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• 2011

This paper describes an analysis of optimal design conditions of multi-mode LDPC(low density parity check) decoder which supports three block lengths (648, 1296, 1944) and four code rates (1/2, 2/3, 3/4, 5/6) for IEEE 802.11n WLAN system. A fixed-point model of LDPC decoder, which adopts min-sum algorithm and layered decoding scheme, is implemented using Matlab. From fixed-point simulation results for various bit-width parameters such as internal bit-width, integer/fractional part bit-widths, optimal design conditions and decoding performance of LDPC decoder are analyzed.

• Transactions of the Korean Society of Mechanical Engineers
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• v.19 no.10
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• pp.2607-2616
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• 1995

The influences of number of spark plug on ignitability, combustion characteristics and combustion promotion effect were examined to establish the design conception of spark ignition system for lean burn. Ignitability was increased remarkably by increasing of number of spark plug at combustion wall. Combustion duration was shortened and maximum combustion pressure was increased in accordance with increasing of spark plug number. Rate of overall combustion promotion considered of combustion duration and combustion pressure was 28% in two point ignition and 40% in four point ignition. It was verified that heat release, heat loss and combustion duration were affected by flame area, heat transfer area and maximum flame travel distance respectively.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.25 no.5
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• pp.841-849
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• 2001

The pixel information of the object was obtained sequentially and pixels were clustered to a label by the line labeling method. Feature points were determined by finding the slope for edge pixels after selecting the fixed number of edge pixels. The slope was estimated by the least square method to reduce the detection error. Once a matching point was determined by comparing the feature information of the object and the pattern, the parameters for translation, scaling and rotation were obtained by selecting the longer line of the two which passed through the matching point from left and right sides. Finally, modified Hausdorff Distance has been used to identify the similarity between the object and the given pattern. The multi-label method was developed for recognizing the patterns with more than one label, which performs the modified Hausdorff Distance twice. Experiments have been performed to verify the performance of the proposed algorithm and method for simple target image, complex target image, simple pattern, and complex pattern as well as the partially hidden object. It was proved via experiments that the proposed image matching algorithm for recognizing the object had a good performance of matching.

• Advances in aircraft and spacecraft science
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• v.1 no.4
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• pp.427-441
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• 2014

Orbit-raising is an important step to place spacecraft from parking orbits into working orbits. Attitude control system design is crucial in the success of orbit-raising. Several text books have discussed this design and focused mainly on the traditional methods based on single-input single-output (SISO) transfer function models. These models are not good representations for many orbit-raising control systems which have multiple thrusters and each thruster has impact on the attitude defined by all outputs. Only one published article is known to use a more suitable multi-input multi-output (MIMO) Euler angle model in spacecraft orbit-raising attitude control system design. In this paper, a quaternion based MIMO model for the orbit-raising attitude control system design is proposed. The advantages of using quaternion based model for orbit-raising control system designs are (a) there is no need for mathematical transformations because the attitude measurements are normally given by quaternion, (b) quaternion based model does not depend on rotational sequences, which reduces the chance of human errors, and (c) the singular point of reduced quaternion model is the farthest from the operational point where linearization is performed. We will show that performance of quaternion model based design will be as good as the performance of Euler angle model based design for orbit-raising problem.

• ETRI Journal
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• v.27 no.1
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• pp.81-88
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• 2005

In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 ${\mu}m$ dual gate oxide CMOS technology.

• Journal of Ship and Ocean Technology
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• v.5 no.1
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• pp.30-37
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• 2001

Ship optimal design is a multi-objective decision-making process and its optimal solution does not exit in general. It is a problem in which the decision-maker is very interested that an effective solution is how to be found which has good characteristic and is substituted for optimal solution in a sense. In the previous methods of multi-objective decision-making, the weighting coefficients are decided from the point of view of individuals which have a bit sub-jective an unilateral behavior. in order to fairly and objectively decide the weighting coeffi-cients, which are considered to be optimal in all system of multi-objective decision-making and satisfactory solution to the decision-maker, the pater presents a method of applying the Technology of the Biggest Entropy. It is proved that the method described in the paper is very feasible and effective be means of a practical example of ship optimal design.