• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.352-358
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• 2016

A 5-phase phase-locked loop (PLL) for USB2.0 applications was implemented by using an all-synthesis technique. The length of the time-to-digital converter for the fine phase detector was halved by the operation of a coarse phase detector that uses 5-phase clocks. The maximum time difference between the rising edges of two adjacent-phase clocks was 6 ps at 480 MHz. The PLL chip in a 65-nm process occupies $0.038mm^2$, consumes 4.8 mW at 1.2 V. The measured rms and peak-to-peak output jitters are 8.6 ps and 45 ps, respectively.

• Proceedings of the KIEE Conference
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• 대한전기학회 1997년도 하계학술대회 논문집 F
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• pp.2016-2019
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• 1997

To solve the low efficiency problem of low-voltage power supplies, it has been studied to replace the schottky barrier diode with the MOSFET synchronous rectifier. In this paper, Phase Shift-Controlled Clamp Mode Zero Voltage Switching-Multi Resonant Converter with Synchronous Rectifier (PSC CM ZVS-MRC with SR) is presented to achieve high efficiency in low-voltage power supplies. The characteristics analysis of synchronous rectifier is established by using the MOSFET equivalent circuit and efficiency comparison is established between the Synchronous Rectifier and the schottky barrier diode. To verify the validity of the analysis, 33W(3.3V, 10A) PSC CM ZVS-MRC with self-driven synchronous rectifier at switching frequency of 1MHz is designed and tested. And it is confirmed that the experimental results are well consistent with the theoretical results. The maximum efficiency of the converter is 83.4% at full load, which is 3.3% higher than conventional schottky diode rectification.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• 제27권4호
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• pp.8-15
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• 2013

This paper proposes a DC-link voltage variation compensation method for a 3-level single phase converter for high-speed trains. Since 3-level NPC(Neutral Point Clamped) type converters have the split DC-link causing the inherent problem of voltage fluctuations in the upper and lower capacitors, reducing the voltage difference between the top and bottom capacitors is required. In this paper, compensation time proportional to the voltage difference is added to PWM switching time to solve the voltage variation. The compensation time is obtained by a PI controller. Simulation results demonstrate the validity of the proposed method.

• Proceedings of the KIEE Conference
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• 대한전기학회 1998년도 하계학술대회 논문집 F
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• pp.2054-2056
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• 1998

A conventional UPS can supply the clean power to the load. However, it may generate input current harmonics and the input power factor can be very poor. Therefore, the UPS itself may be a power interruption. This paper provides multifunctional converter of using single phase UPS. The proposed UPS can supply the clean power to the load without polluting the mains power system. The multi-functional converter provides battery charging, var compensation and harmonic suppression simultaneously. It was simulated to verify this work.

• Journal of Power Electronics
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• 제16권1호
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• pp.173-181
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• 2016

In this paper, a new technique for harmonic optimization in cascaded H-bridge 7-level inverters is proposed. The suggested strategy is based on minimizing an objective function which simultaneously optimizes the converter utilization and Total Harmonic Distortion (THD). The Switch Utilization Ratio (SUR) is formulized for both the phase and line-line voltages of a 7-level inverter and is considered in the final objective functions. Based upon the SUR formula, utilization ratio enhancement will reduce the value of feeding DC links, which improves the efficiency and lifetime of the circuit components due to lower voltage stresses and losses. In order to achieve more effective solution in different modulation indices, it is assumed that the DC sources can be altered. Experimental validation is presented based on a three-phase 7-level inverter prototype.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• 제12권1호
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• pp.1-6
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• 2019

An extremely small size multi-loop phase-locked loop(PLL) keeping phase noise performances has been proposed. It has been designed to have the loop filter made of small single capacitor with multiple Frequency Voltage Converters (FVCs) because the main goal is to make the size of the proposed PLL extremely small. Multiple FVCs which are connected to voltage controlled oscillator(VCO) make multiple negative feedback loops in PLL. Those multiple negative feedback loops enable the PLL with the loop filter made of an extremely small size single capacitor operate stably. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the 1.6ps jitter and $10{\mu}s$ locking time.

• The Transactions of the Korean Institute of Power Electronics
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• 제27권3호
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• pp.247-255
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• 2022

This paper proposes a multiphase interleaved zero-voltage-transition boost converter with a single soft-switching cell for high-voltage DC-DC converter (HDC) of fuel cell systems. The proposed single soft-switching cell structure can reduce the system volume by minimizing the passive and active elements added even in the multiphase-interleaved structure. To analyze the feasibility of the proposed structure, this paper mathematically analyzes the operation modes of the converter with the proposed single soft-switching cell structure and presents guidelines for design and considerations. In addition, the feasibility of the 210[kW] HDC was confirmed through PSIM simulation, and the system volume reduction of up to 10.48% was confirmed as a result of the 5[kW] HDC test-bed experiment considering the fuel cell system. Through this, the validity of the proposed structure was verified.

• The Journal of the Korea institute of electronic communication sciences
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• 제7권6호
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• pp.1429-1435
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• 2012

DC-DC converter commonly used in photovoltaic systems, fuel cell systems and electric vehicles is a boost converter. The interleaved boost converter, connected in parallel by several boost converters and operated by the phase difference to reduce the input and output current ripple, has been widely used in recent years. Because of small input and output current ripples, the circuit can reduce the size of the input and output capacitors. Thus, instead of conventional electrolytic capacitor, the film capacitor with high reliability can be used and this is the life and reliability of the entire system can be improved. In this paper, the output current ripple formulas of the multi-stage interleaved boost converter are derived, and the characteristics in accordance with duty are found out. In order to verify the abovementioned contents, the derived results will make a comparison with the calculated values by using PSIM tool.

• The Transactions of The Korean Institute of Electrical Engineers
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• 제65권10호
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• pp.1655-1663
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• 2016

Recently the researches on Modular Multi-level Converter (MMC) are being highlighted because high quality and efficient power transmission are key issues in the High Voltage Direct Current (HVDC) transmission system. This paper proposes an improved pre-charging method for the sub-module capacitors in MMC that operates in Nearest Level Control (NLC) modulation. The proposed method does not require additional circuits or Pulse Width Modulation (PWM) techniques. The feasibility of proposed method was verified through computer simulations for a scaled 3-phase 10kVA MMC with 12 sub-modules per each arm. Hardware experiments with a scaled prototype were performed in the lab to confirm the simulation results.

• Journal of Power Electronics
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• 제15권4호
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• pp.1035-1046
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• 2015

This study presents a practical implementation of a multi-mode two-phase interleaved boost converter for fuel cell electric vehicle application. The main operating modes, which include two continuous conducting modes and four discontinuous conducting modes, are discussed. The boundaries and transitions among these modes are analyzed with consideration of the inductor parasitic resistance. The safe operational area is analyzed through a comparison of the different operating modes. The output voltage and power characteristics with open-loop or closed-loop operation are also discussed. Key performance parameters, including the DC voltage gain, input ripple current, output ripple voltage, and switch stresses, are presented and supported by simulation and experimental results.