• 대한산업공학회지
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• 제36권3호
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• pp.154-163
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• 2010

Process monitoring of output variables affecting final performance have been mainly executed in semiconductor manufacturing process. However, even earlier detection of causes of output variation cannot completely prevent yield loss because a number of wafers after detecting them must be re-processed or cast away. Semiconductor manufacturers have put more attention toward monitoring process inputs to prevent yield loss by early detecting change-point of the process. In the paper, we propose the method to efficiently monitor functional input variables in multi-phase semiconductor manufacturing process. Measured input variables in the multi-phase process tend to be of functional structured form. After data pre-processing for these functional input data, change-point analysis is practiced to the pre-processed data set. If process variation occurs, key variables affecting process variation are selected using contribution plot for monitoring efficiency. To evaluate the propriety of proposed monitoring method, we used real data set in semiconductor manufacturing process. The experiment shows that the proposed method has better performance than previous output monitoring method in terms of fault detection and process monitoring.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.143-146
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• 2016

A new area-efficient multi-phase clock frequency multiplier is presented. The proposed fractional-ratio frequency multiplying DLL (FFMDLL) is implemented in a 65 nm CMOS process and occupies an active area of just $0.01mm^2$. The proposed FFMDLL provides 8-phase output clocks and achieves a frequency range of 0.6-1.0 GHz with programmable multiplication ratios of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. It achieves an effective peak-to-peak jitter of 5 ps and dissipates 3.4 mW from a 1.0 V supply at 1 GHz.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.16-21
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• 2006

A simple doping method to fabricate a very thin channel body of the p-type FinFETs with a 20 nm gate length by solid-phase-diffusion (SPD) process was developed. Using the poly-boron-films (PBF) as a novel diffusion source of boron and the rapid thermal annealing (RTA), the p-type sourcedrain extensions of the FinFET devices with a threedimensional structure were doped. The junction properties of boron doped regions were investigated by using the $p^+-n$ junction diodes which showed excellent electrical characteristics. Single channel and multi-channel p-type FinFET devices with a gate length of 20-100 nm was fabricated by boron diffusion process using PBF and revealed superior device scalability.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.387-394
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• 2016

This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in a 65 nm CMOS process, the proposed DLL occupies $0.0432mm^2$, and consumes 3.7 mW from a 1.2-V supply at 2 GHz.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.352-358
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• 2016

A 5-phase phase-locked loop (PLL) for USB2.0 applications was implemented by using an all-synthesis technique. The length of the time-to-digital converter for the fine phase detector was halved by the operation of a coarse phase detector that uses 5-phase clocks. The maximum time difference between the rising edges of two adjacent-phase clocks was 6 ps at 480 MHz. The PLL chip in a 65-nm process occupies $0.038mm^2$, consumes 4.8 mW at 1.2 V. The measured rms and peak-to-peak output jitters are 8.6 ps and 45 ps, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.52-58
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• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

• 비파괴검사학회지
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• 제29권6호
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• pp.550-556
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• 2009

In an application of a time reversal(TR) focusing of array transducer on a defect inside the test material, we employ a new time delay focusing technique based the TR process. In order to realize this idea, a multi-channel ultrasonic system is constructed capable of applying necessary time delays to each channel. The TR-based focusing procedure first measures the backscattered signals after firing one of the array elements. A phase slope method is then used to determine the time-of-flights of the backscattered signals received by all elements of the array. These time delays are used to adjust the time of excitation of the elements for transmission focusing on the defect. In addition to the TR focusing, the classical phased array focusing is also considered for comparison. Experimental results show that the TR-based time delay focusing produces much stronger backscattered signals than the phased array focusing, demonstrating the enhanced capability of the TR focusing.

• 한국인터넷방송통신학회논문지
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• 제24권4호
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• pp.121-127
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• 2024

본 논문에서는 다중 위상배열 구조의 위성통신단말 송수신모듈 적용을 위한 핵심부품인 FEM(Front-End Module) MMIC를 구성품인 전력증폭기 (PA: Power Amplifier)와 저잡음증폭기 (LNA: Low Noise Amplifier)를 단일칩으로 설계하여 제작, 검증하였다. Win-semiconductors사의 화합물반도체 공정인 GaAs PP10 (100nm) 공정을 사용하여 제작하였으며, 전용 시험보드를 이용하여 운용 주파수 대역 7.2-10.5GHz 동작, 출력 1W, 잡음지수 1.5dB 이하의 특성을 확보하였다. 개발된 FEM MMIC는 단일칩으로도 활용이 가능하며, 구성품인 PA, LNA도 각각의 소자로도 활용이 가능하다. 개발된 소자는 해외 부품의 국산화 대체와 X대역을 사용하는 민수/군수의 다양한 응용분야에서 사용될 것이다.

• 대한전자공학회논문지SD
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• 제44권2호
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• pp.19-24
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• 2007

최근 대용량 데이터 전송이 이루어지면서 하드웨어의 복잡성과 전력, 가격 등의 이유로 인하여 입력데이터와 클럭을 함께 수신 단으로 전송하는 병렬버스 기법보다는 시리얼 링크 기법이 메모리 인터페이스에 많이 사용되고 있다. 시리얼 링크 기법은 병렬버스 기법과는 달리 클럭을 제외한 데이터 정보만을 수신단으로 보내는 방식이다. 클럭 및 데이터 복원 회로(clock and data recovery 혹은 CDR)는 시리얼 링크의 핵심 블록으로, 본 논문에서는 그래픽 DRAM 인터페이스용의 5.4Gb/s half-rate bang-bang 클럭 및 데이터 복원회로를 설계하였다. 이 회로는 half-rate bang-bang 위상검출기, current-mirror 전하펌프, 이차 루프필터, 및 4단의 차동 링타입 VCO로 구성되었다. 위상 검출기의 내부에서 반 주기로 DeMUX된 데이터를 복원할 수 있게 하였고, 전체 회로의 용이한 검증을 위해 MUX를 연결하여, 수신된 데이터가 제대로 복원이 되는지를 확인하였다. 설계한 회로는 66㎚ CMOS 공정파라미터를 기반으로 설계 및 layout하였고, post-layout 시뮬레이션을 위해 5.4Gb/s의 $2^{13}-1$ PRBS 입력데이터를 사용하였다. 실제 PCB 환경의 유사 기생성분을 포함하여 시뮬레이션 한 결과, 10psRMS 클럭 지터 및 $40ps_{p-p}$ 복원된 데이터 지터 특성을 가지고, 1.8V 단일 전원전압으로부터 약 80mW 전력소모를 보인다.