• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.4
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• pp.281-290
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• 2012

This paper describes a Cross-regulation characteristics of a multi-output LLC resonant converter widely used in consumer electronics. The output characteristics of the multi-output LLC converter is derived from the assumption that the current and voltage in the resonant network is sinusoidal and the duty loss exists. The simulation and experimental results are provided to verify the theoretic results.

• The KIPS Transactions:PartA
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• v.19A no.1
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• pp.45-50
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• 2012

The demand for faster execution time and lower energy consumption has compelled architects of embedded processors to customize it to the needs of their target applications. These processors consequently provide a rich set of specialized instructions in order to enable programmers to access these features. Such an instruction is typically a $multi$-$output$ $instruction$ (MOI), which outputs multiple results parallely in order to exploit inherent underlying hardware parallelism. Earlier study has exhibited that MOIs help to enhance performance in aspect of instruction counts and code size. However the earlier algorithm does not consider the register pressure. So, some selected MOIs introduce register spill/reload code that increases the code size and instruction count. To attack this problem, we introduce a novel iterated instruction selection algorithm based on the register pressure of each selected MOIs. The experimental results show the suggested algorithm achieves 3% code-size reduction and 2.7% speed-up on average.

• ETRI Journal
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• v.30 no.1
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• pp.113-128
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• 2008

Turbo codes are extensively used in current communications standards and have a promising outlook for future generations. The advantages of software defined radio, especially dynamic reconfiguration, make it very attractive in this multi-standard scenario. However, the complex and power consuming implementation of the maximum a posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal. This work introduces an ASIP architecture for the MAP algorithm, based on a dual-clustered VLIW processor. It displays the good performance of application specific designs along with the versatility of processors, which makes it compliant with leading edge standards. The machine deals with multi-operand instructions in an innovative way, the fetching and assertion of data is serialized and the addressing is automatized and transparent for the programmer. The performance-area trade-off of the proposed architecture achieves a throughput of 8 cycles per symbol with very low power dissipation.

• Proceedings of the Korea Information Processing Society Conference
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• 2008.05a
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• pp.530-531
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• 2008

많은 DSP 등에서 Multi-Output Instructions(MOI)를 지원하나 이를 사용할 수 있는 컴파일러가 없다. 그래서 기존연구에서 이 문제를 해결하는 새로운 코드 생성 알고리즘을 개발하여 소개하였다. 하지만, 이 논문에서 제시한 방법은 많은 제약이 있어, 본 논문에서는 기존 논문에서 사용한 MOI를 위한 compiler grammar rule description을 확장하고, 알고리즘을 변경하여 기존에 제안된 방법이 해결할 수 없었던 MOI 들까지 모두 컴파일러에서 처리할 수 있도록 하였다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.132-140
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• 1994

In this paper, we consider the area-minimal implementation of the instruction decoder for microprogrammed processors such as modern CISC-type microprocessor. We formulate it as a constrained output encoding problem and, based on simulated annealing algorithm, propose efficient heuristic solution methods both for PLA and multi-level implementation of the decoder. Experimental results on various examples show that our methods produce, on the average, 10~40% reduction of the number of product terms for the PLA implementations and 9.8~34.4% reduction of the number of literal for the multi-level implementations compared to the results of random encoding method.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.10
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• pp.1081-1087
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• 2008

This paper describes limitations and solutions of the existing processor-monitoring concept for a military supersonics aircraft Flight Control Computer (FLCC) equipped with modern architecture processor to perform the system integration test. Safecritical FLCC integration test, which requires automatic test for thousands of test cases and real-time input/output test condition generation, depends on the processor-monitoring device called Processor Interface (PI). The PI, which relies upon on the FLCC processor's external address and data-bus data, has some limitations due to multi-fetching capability of the modern sophisticated military processors, like C6000's VLIW (Very-Long Instruction Word) architecture and PowerPC's Superscalar architecture. Several techniques for limitations were developed and proper monitoring approach was presented for modem processor-adopted FLCC system integration test.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.220-223
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• 2006

In this paper, we studied about the level controller of optical signal with 40 channels by 4 VOA(Variable Optical Attenuator) with 12 channels. Total 8 microprocessors control 40 chamois for control of optical signal level so that a microprocessor controls 5 channels each. Moreover a microprocessor was added to communicate with outside and transfer instruction to each microprocessor. The output optical signal is measured and VOA is controlled as a result of it. The VOA outputs is inputted into PD(Photo Detector) at once. We could control multi-channel optical signals simply like this.