• Title/Summary/Keyword: Multi-level switching

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A Study on Optical Transport Platform on ATCA

  • Yang, Choong-Reol;Ko, Je-Soo
    • Journal of the Optical Society of Korea
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    • v.11 no.4
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    • pp.145-148
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    • 2007
  • In this paper, we discuss a study on Advanced TCA(ATCA) based 40 Gbps level Optical transport platform having 120 Gbps(12, 10 Gbps modules) switching capacity as an OTP based large capacity multi service technology. The ATCA-based OTP(Optical Transport Platform) is composed of OTH(Optical Transport Hierarchy) 10 or 40 Gbps client signal interface module, OTH 10 Gbps transport module, high-rate OTH unit switch, system processor, and can be installed in ATCA platform.

Low Power Logic Synthesis based on XOR Representation of Boolean Functions (부울함수의 XOR 표현을 기초로 한 저전력 논리합성)

  • Hwang, Min;Lee, Guee-Sang
    • Proceedings of the IEEK Conference
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    • 2000.11b
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    • pp.337-340
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    • 2000
  • In this paper, we put forth a procedure that target low power logic synthesis based on XOR representation of Boolean functions, and the results of synthesis procedure are a multi-level XOR form with minimum switching activity. Specialty, this paper show a method to extract the common cubes or kernels by Boolean matrix and rectangle covering, and to estimate the power consumption in terms of the extracted common sub-functions.

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Low Power Design Using the Extraction of kernels (커널 추출을 이용한 저전력설계)

  • 이귀상;정미경
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.369-372
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    • 1999
  • In this paper, we propose a new method for power estimation in nodes of multi-level combinational circuits and describe its application to the extraction of common expressions for low power design. It is assumed that each node is implemented as a complex gate and the capacitance and the switching activity of the nodes are considered in the power estimation. Extracting common expressions which is accomplished mostly by the extraction of kernels, can be transformed to the problem of rectangle covering. We describe how the newly proposed estimation method can be applied to the rectangle covering problem and show the experimental results with comparisons to the results of SIS-1.2.

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Single Soft-Switching Multi-Level Energy Recovery Circuit Driver for Plasma Display Panel (플라즈마 디스플레이 채널을 위한 단일 소프트-스위칭 다단계 에너지 회수 회로 드라이버)

  • Jacobo Aguillon-Garcia;Moon Gun-Woo
    • Proceedings of the KIPE Conference
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    • 2006.06a
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    • pp.413-416
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    • 2006
  • The power source of an AC-PDP fur sustainer circuit is operated in high-voltage and high frequency switching during the process required to achieve the gas discharge current to generate light in a PDP panel. Since PDP has the characteristics of a pure capacitive load, the displacement current that occurs during charge and discharge generates considerable reactive power. An auxiliary circuitry called Energy Recovery Circuit (ERC) reduces the capacitive displacement current. However, this auxiliary topology also bears high stress in its components. In this paper, a multilevel voltage wave shaping sustainer circuit with auxiliary ERC characteristics for an AC-PDP driver is proposed. A comparative analysis and experimental results are presented.

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DC-link Voltage Ripple Compensation Method for Single Phase 3-level PWM Converters (단상 3-레벨 PWM 컨버터를 위한 중성점 전압 변동 보상 기법)

  • Lee, Hee-Myun;Lee, Dong-Myung
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.27 no.4
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    • pp.8-15
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    • 2013
  • This paper proposes a DC-link voltage variation compensation method for a 3-level single phase converter for high-speed trains. Since 3-level NPC(Neutral Point Clamped) type converters have the split DC-link causing the inherent problem of voltage fluctuations in the upper and lower capacitors, reducing the voltage difference between the top and bottom capacitors is required. In this paper, compensation time proportional to the voltage difference is added to PWM switching time to solve the voltage variation. The compensation time is obtained by a PI controller. Simulation results demonstrate the validity of the proposed method.

A Possible Path per Link CBR Algorithm for Interference Avoidance in MPLS Networks

  • Sa-Ngiamsak, Wisitsak;Varakulsiripunth, Ruttikorn
    • 제어로봇시스템학회:학술대회논문집
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    • 2004.08a
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    • pp.772-776
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    • 2004
  • This paper proposes an interference avoidance approach for Constraint-Based Routing (CBR) algorithm in the Multi-Protocol Label Switching (MPLS) network. The MPLS network itself has a capability of integrating among any layer-3 protocols and any layer-2 protocols of the OSI model. It is based on the label switching technology, which is fast and flexible switching technique using pre-defined Label Switching Paths (LSPs). The MPLS network is a solution for the Traffic Engineering(TE), Quality of Service (QoS), Virtual Private Network (VPN), and Constraint-Based Routing (CBR) issues. According to the MPLS CBR, routing performance requirements are capability for on-line routing, high network throughput, high network utilization, high network scalability, fast rerouting performance, low percentage of call-setup request blocking, and low calculation complexity. There are many previously proposed algorithms such as minimum hop (MH) algorithm, widest shortest path (WSP) algorithm, and minimum interference routing algorithm (MIRA). The MIRA algorithm is currently seemed to be the best solution for the MPLS routing problem in case of selecting a path with minimum interference level. It achieves lower call-setup request blocking, lower interference level, higher network utilization and higher network throughput. However, it suffers from routing calculation complexity which makes it difficult to real task implementation. In this paper, there are three objectives for routing algorithm design, which are minimizing interference levels with other source-destination node pairs, minimizing resource usage by selecting a minimum hop path first, and reducing calculation complexity. The proposed CBR algorithm is based on power factor calculation of total amount of possible path per link and the residual bandwidth in the network. A path with high power factor should be considered as minimum interference path and should be selected for path setup. With the proposed algorithm, all of the three objectives are attained and the approach of selection of a high power factor path could minimize interference level among all source-destination node pairs. The approach of selection of a shortest path from many equal power factor paths approach could minimize the usage of network resource. Then the network has higher resource reservation for future call-setup request. Moreover, the calculation of possible path per link (or interference level indicator) is run only whenever the network topology has been changed. Hence, this approach could reduce routing calculation complexity. The simulation results show that the proposed algorithm has good performance over high network utilization, low call-setup blocking percentage and low routing computation complexity.

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Relation between Resistance and Capacitance in Atomically Dispersed Pt-SiO2 Thin Films for Multilevel Resistance Switching Memory (Pt 나노입자가 분산된 SiO2 박막의 저항-정전용량 관계)

  • Choi, Byung Joon
    • Korean Journal of Materials Research
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    • v.25 no.9
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    • pp.429-434
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    • 2015
  • Resistance switching memory cells were fabricated using atomically dispersed Pt-$SiO_2$ thin film prepared via RF co-sputtering. The memory cell can switch between a low-resistance-state and a high-resistance-state reversibly and reproducibly through applying alternate voltage polarities. Percolated conducting paths are the origin of the low-resistance-state, while trapping electrons in the negative U-center in the Pt-$SiO_2$ interface cause the high-resistance-state. Intermediate resistance-states are obtained through controlling the compliance current, which can be applied to multi-level operation for high memory density. It is found that the resistance value is related to the capacitance of the memory cell: a 265-fold increase in resistance induces a 2.68-fold increase in capacitance. The exponential growth model of the conducting paths can explain the quantitative relationship of resistance-capacitance. The model states that the conducting path generated in the early stage requires a larger area than that generated in the last stage, which results in a larger decrease in the capacitance.

High Efficiency Strategy of High Input Voltage SMPS (고전압 입력용 SMPS의 고효율 전략)

  • Woo, Dong-Young;Park, Seong-Mi;Park, Sung-Jun
    • Journal of the Korean Society of Industry Convergence
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    • v.22 no.3
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    • pp.365-371
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    • 2019
  • Recently, the demonstration and research on the power transmission using high voltage DC such as HVDC(High Voltage DC), Smart Grid, DC transmission and distribution have been actively conducted. In order to control the power converter in high-voltage DC power transmission system, SMPS(Switching Modulation Power Supply) for power converter control using high-voltage DC input is essential. However, the demand for high-pressure SMPS is still low, so the development is not enough. In the low-output SMPS using the high-voltage input, it is difficult to achieve high efficiency due to the switching transient loss especially at light load. In this paper, we propose a new switching scheme for high power SMPS control for low output power. The proposed method can provide better efficiency increase effect in the light load region compared to the existing PWM method. To verify the feasibility of the proposed method, a 40 W SMPS for HVDC MMC(Modulation Multi-level Converter) was designed and verified by simulation.

A Study on Muti-Level Type Charging Technique for Ocean Facility (해양 시설물용 다중 레벨 방식 충전기법에 관한 연구)

  • Oh, Jin-Seok;Kwak, Jun-Ho
    • Journal of Advanced Marine Engineering and Technology
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    • v.34 no.6
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    • pp.906-913
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    • 2010
  • Recently, lots of researches are carried out to develop hybrid power generation system for ocean facility. Normally, the stand-alone type power system is used in the ocean facility, which is influenced by weather condition. To improve the efficiency, a various charging strategy with switching algorithm has been studied. In this paper, the power system using multi-level type is proposed. The simulation results based on actual data of photovoltaic and wave hybrid power system are presented. The results show that the rate of charging time is increased 5~11% and 7~47% respectively to compare the conventional technique.

Effects of Gradient Switching Noise on ECD Source Localization with the EEG Data Simultaneously Recorded with MRI (MRI와 동시에 측정한 뇌전도 신호로 전류원 국지화를 할 때 경사자계 유발 잡음의 영향 분석)

  • Lee H. R.;Han J. Y.;Cho M. H.;Im C. H.;Jung H. K.;Lee S. Y.
    • Investigative Magnetic Resonance Imaging
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    • v.7 no.2
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    • pp.108-115
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    • 2003
  • Purpose : To evaluate the effect of the gradient switching noise on the ECD source localization with the EEG data recorded during the MRI scan. Materials and Methods : We have fabricated a spherical EEG phantom that emulates a human head on which multiple electrodes are attached. Inside the phantom, electric current dipole(ECD) sources are located to evaluate the source localization error. The EEG phantom was placed in the center of the whole-body 3.0 Tesla MRI magnet, and a sinusoidal current was fed to the ECD sources. With an MRI-compatible EEG measurement system, we recorded the multi channel electric potential signals during gradient echo single-shot EPI scans. To evaluate the effect of the gradient switching noise on the ECD source localization, we controlled the gradient noise level by changing the FOV of the EPI scan. With the measured potential signals, we have performed the ECD source localization. Results : The source localization error depends on the gradient switching noise level and the ECD source position. The gradient switching noise has much bigger negative effects on the source localization than the Gaussian noise. We have found that the ECD source localization works reasonably when the gradient switching noise power is smaller than $10\%$ of the EEG signal power. Conclusion : We think that the results of the present study can be used as a guideline to determine the degree of gradient switching noise suppression in EEG when the EEG data are to be used to enhance the performance of fMRI.

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