• 한국통계학회:학술대회논문집
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• 한국통계학회 2002년도 춘계 학술발표회 논문집
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• pp.19-24
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• 2002

The two-way balanced one-level rotation design has been discussed (Park, Kim and Choi, 2001), where the two-way balancing is done on interview time in monthly sample and rotation group. We extend it to three-way balanced multi-level design under the most general rotation system. The three-way balancing is accomplished on interview time not only in monthly sample and rotation group but also in recall time. We present the necessary condition and rotation algorithm which guarantee the three-way balancing. We propose multi-level composite estimators (MCE) from this design and derive their variances and mean squared errors (MSE), assuming the correlation from the measurements of the same sample unit and three types of biases in monthly sample.

• 한국전산구조공학회:학술대회논문집
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• 한국전산구조공학회 2002년도 가을 학술발표회 논문집
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• pp.255-262
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• 2002

In this paper, an improved multi-objective optimmum design method is proposed. And it is applied to steel frames under seismic loads. The multi-objective optimization problem is formulated with three optimality criteria, namely, minimum structural weight and maximum strain energy and stability. The Pareto curve can be obtained by performing the multi-objective optimization for multistory shear buildings. In order to efficiently solve the multi-objective optimization problem the decomposition method that separates both system-level and element-level is used. In addition, various techniques such as effective reanalysis technique with respect to intermediate variables and sensitivity analysis using an automatic differentiation (AD) we incorporated. Moreover, the relationship function among section properties induced from the profile is used in order to link system-level and element level. From the results of numerical investigation, it may be stated that the proposed method will lead to the more rational design compared with the conventional one.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.553-556
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• 2004

In this paper, we present a new efficient multi-level hardware/software partitioning algorithm for system-on-a-chip design. Originally the multi-level partitioning algorithm are proposed to enhance the performance of previous iterative improvement partitioning algorithm for large scale circuits. But when designing very complex and heterogeneous SoCs, the HW/SW partitioning decision needs to be made prior to refining the system description. In this paper, we present a new method, based on multi-level algorithm, which can cover SoC design. The different variants of algorithm are evaluated by a randomly generated test graph. The experimental results on test graphs show improvement average $9.85\%$ and $8.51\%$ in total communication costs over FM and CLIP respectively.

• 전자공학회논문지C
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• 제34C권3호
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• pp.11-22
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• 1997

This paper presents the design and implementation of an efficient algorithm for detecting untestable paths in multi-level circuits. Transforming multi-level circuit into a multiplexor-based one through BDD(binary decision diagram)construction, the proposed algorithm detects untestable paths in the transformed circuits. By constructing ENF (equivalent normal form) only for reconvergent paths, the proposed system detects and removes untestable paths efficiently in terms of the run-time and memory usage. Experimental results for MCNC/ISCAS benchmark circuits show that the system efficiently detects and removes untestable paths. The run-time and memory usage have been reduced by 37.7% and 60/9%, respectively, comapred to the previous methods.

• 한국전산구조공학회:학술대회논문집
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• 한국전산구조공학회 2000년도 봄 학술발표회논문집
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• pp.177-186
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• 2000

An improved multi-level（IML) optimization algorithm using automatic differentiation (AD) for multi-objective optimum design of framed structures is proposed in this paper. In order to optimize the steel frames under seismic load, two main objective functions need to be considered for minimizing the structural weight and maximizing the strain energy. For the efficiency of the proposed algorithm, multi-level optimization techniques using decomposition method that separately utilizes both system-level and element-level optimizations and an artificial constraint deletion technique are incorporated in the algorithm. And also to save the numerical efforts, an efficient reanalysis technique through approximated structural responses such as moments, frequencies, and strain energy with respect to intermediate variables is proposed in the paper. Sensitivity analysis of dynamic structural response is executed by AD that is a powerful technique for computing complex or implicit derivatives accurately and efficiently with minimal human effort. The efficiency and robustness of the IML algorithm, compared with a plain multi-level (PML) algorithm, is successfully demonstrated in the numerical examples.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권1호
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• pp.55-60
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• 2010

For battery-powered device applications, which grow rapidly in the electronic market today, low-power becomes one of the most important design issues of CMOS VLSI circuits. A multi-VDD system, which uses more than one power-supply voltage in the same system, is an effective way to reduce the power consumption without degrading operating speed. However, in the multi-VDD system, level converters should be inserted to prevent a large static current flow for the low-to-high conversion. The insertion of the level converters induces the overheads of power consumption, delay, and area. In this paper, we propose a new level converter which can provide the level up/down conversions for the various input and output voltages. Since the proposed level converter uses only one power-supply voltage, it has an advantage of reducing the complexity in physical design. In addition, the proposed level converter provides lower power and higher speed, compared to existing level converters.

• 한국건축시공학회:학술대회논문집
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• 한국건축시공학회 2016년도 춘계 학술논문 발표대회
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• pp.113-114
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• 2016

This paper proposes a technical requirements analysis of implementation of multi-trade prefabrication. Recently, there has been a rise in the use of prefabrication to minimize on-site work for time reduction to increase productivity. Prefabrication technique is evolved into multi-trade prefabrication combining other trades from single-trade prefabrication. For implementation of new technique, not only itself but complementary techniques have to be prepared. In this paper, MEP corridor rack, a major item of multi-trade prefabrication, was implemented in the test bed and its process was analyzed to find out technical requirements. As a result, comparatively high level of IT technique was required for efficient use of multi-trade prefabrication in design, lifting and construction phase. In design phase, component level of BIM library was needed for manufacturing; and in lifting phase, BIM-based site logistics process was required. Also in construction phase, laser scanning was implemented for gathering shape and geometry of the wall and slab that were attached to multi-trade prefabrication module.

• Industrial Engineering and Management Systems
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• 제15권4호
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• pp.374-384
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• 2016

The efficiency of a supply chain can be extremely affected by its design which includes determining the flow pattern of material from suppliers to costumers, selecting the suppliers, and defining the opened facilities in network. In this paper, a multi-objective multi-echelon multi-product supply chain design model is proposed in which several suppliers, several manufacturers, several distribution centers as different stages of supply chain cooperate with each other to satisfy various costumers' demands. The multi-objectives of this model which considered simultaneously are 1-minimize the total cost of supply chain including production cost, transportation cost, shortage cost, and costs of opening a facility, 2-minimize the transportation time from suppliers to costumers, and 3-maximize the service level of the system by minimizing the maximum level of shortages. To configure this model a graph theoretic approach is used by considering channels among each two facilities as links and each facility as the nodes in this configuration. Based on complexity of the proposed model a multi-objective Pareto-based vibration damping optimization (VDO) algorithm is applied to solve the model and finally non-dominated sorting genetic algorithm (NSGA-II) is also applied to evaluate the performance of MOVDO. The results indicated the effectiveness of the proposed MOVDO to solve the model.

• 품질경영학회지
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• 제43권1호
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• pp.31-42
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• 2015

Purpose: System consists of a lot of units with coherent function. In design phase, various units could be considered with the same function. In this study, we consider the alternative units with the same function and redundancy allocation to maximize system reliability in multi level system. Methods: The redundancy allocation problem with the alternative units in multi level system is formulated. Memetic algorithm(MA) is proposed to optimize the redundancy allocation problem. In addition, the performance of the proposed algorithm is explained by a numerical experiment. Results: MA showed better results than genetic algorithm(GA) and the convergence of the solutions in MA was also faster than GA. In addition, we could know from experiment that system reliability is increased and the chosen unit for redundancy allocation is changed if cost limit is increased. Conclusion: The chose unit for redundancy allocation is changed as resource constraints. It means we need to consider the alternative units in system design. In the future, we need to consider various problem related to redundancy allocation in multi level system and develop the better method to enhance search performance.

• Journal of Power Electronics
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• 제9권4호
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• pp.593-603
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• 2009

This paper proposes and describes the design and operational principles of a three-phase three-level nine switch voltage source inverter. The proposed topology consists of three bi-directional switches inserted between the source and the full-bridge power switches of the classical three-phase inverter. As a result, a three-level output voltage waveform and a significant suppression of load harmonics contents are obtained at the inverter output. The harmonics content of the proposed multilevel inverter can be reduced by half compared with two-level inverters. A Fourier analysis of the output waveform is performed and the design is optimized to obtain the minimum total harmonic distortion. The full-bridge power switches of the classical three-phase inverter operate at the line frequency of 50Hz, while the auxiliary circuit switches operate at twice the line frequency. To validate the proposed topology, both simulation and analysis have been performed. In addition, a prototype has been designed, implemented and tested. Selected simulation and experimental results have been provided.