• Proceedings of the Optical Society of Korea Conference
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• 2007.07a
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• pp.187-188
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• 2007

Four kinds of mirror substrates with same surface roughness were fabricated. On those substrates, a dielectric multi-layer coating with high reflectivity was deposited by ion beam sputtering technique. Most of the fused silica mirrors showed lower scattering than the ZERODUR mirrors one, which deposited on substrates similar in surface roughness. The ZERODUR mirrors scattering strongly depend on the micro-structure of $Ta_2O_5/SiO_2$ thin films wear deposited on ZERODUR substrates.

• Journal of the Korean Ceramic Society
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• v.46 no.2
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• pp.146-154
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• 2009

It is necessary to minimize the thickness of Ni inner electrode layer and to improve the coverage of inner electrode, for the purpose of developing the ultra high-capacity multi layered ceramic capacitor (MLCC). Thus, low temperature sintering of dielectric $BaTiO_3$ ceramic should be precedently investigated. In this work, the relationship between dielectric properties of MLCC and batch condition such as mixing and milling methods was investigated in the $BaTiO_3$(BT)-Dy-Mg-Ba system with borosilicate glass as a sintering agent. In addition, several chip properties of MLCC manufactured by low temperature sintering were compared with conventionally manufactured MLCC. It was found that low temperature sintered MLCC showed better DC-bias property and lower aging rate. It was also confirmed that the thickness of Ni inner electrode layer became thinner and the coverage of inner electrode was improved through low temperature sintering.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.253-253
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• 2008

Recently, high performance microelectronic devices are designed in multi-layer structure in order to make dense wiring of metal conductors in compact size. For making dense wiring of metal conductors, we investigated CTE and peel strength of dielectric materials for next generation PCB. It is an object of this research to develop an epoxy resin composition for an interlayer insulating material exhibiting low CTE and high peel strengnth and making an insulating layer thinner.

• Journal of Aerospace System Engineering
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• v.15 no.6
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• pp.59-65
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• 2021

In this paper, the transmission characteristics of the multi-layered composite material with wire mesh and honeycomb core for aircraft applications have been analyzed with the proposed method. The proposed method converts the conductive wire mesh into effective layer, while for the dielectric honeycomb core, effective permittivity has been derived based on volume fraction with the proposed method. The proposed method has been verified through comparison with full-wave simulation and revealed excellent. In addition, the calculation time of the proposed method is a few order of magnitude faster in comparison with the full-wave simulation.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.53-58
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• 2023

The storage capacity of 3D-NAND flash memory has been enhanced by the multi-layer dielectrics. The deposition process has become more challenging due to the tight process margin and the demand for accurate process control. To reduce product costs and ensure successful processes, process diagnosis techniques incorporating artificial intelligence (AI) have been adopted in semiconductor manufacturing. Recently there is a growing interest in process diagnosis, and numerous studies have been conducted in this field. For higher model accuracy, various process and sensor data are required, such as optical emission spectroscopy (OES), quadrupole mass spectrometer (QMS), and equipment control state. Among them, OES is usually used for plasma diagnostic. However, OES data can be distorted by viewport contamination, leading to misunderstandings in plasma diagnosis. This issue is particularly emphasized in multi-dielectric deposition processes, such as oxide and nitride (ON) stack. Thus, it is crucial to understand the potential misunderstandings related to OES data distortion due to viewport contamination. This paper explores the potential for misunderstanding OES data due to data distortion in the ON stack process. It suggests the possibility of excessively evaluating process drift through comparisons with a QMS. This understanding can be utilized to develop diagnostic models and identify the effects of viewport contamination in ON stack processes.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.171-174
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• 1994

The drive towards ultra-large-scale integrated circuits a continuous intermetal dielectric films for multi layer interconection. Optimum condition of remote plasma enhanced chemical vapour deposition(RPECVD) was achieved by orthogonal array method. Chracteristics of SiO$_2$ films deposited by using remote PECVD with N$_2$O gas were investigated. Etching rate of SiO$_2$ films in P-echant was about 6[A/s] that was the same as the thermal oxide. The films a showed high breakdown voltage of 7(MV/cm) and a resistivity of Bx10$\^$13/[$\Omega$cm] at 7(MV/cm). The interface Trap density of SiO$_2$ has been shown excel lent properties of 5x10$\^$10/[/$\textrm{cm}^2$eV]. It was observed that the dielectric constant dropped to a value of 4. 29 for 150 [W] RF power.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.4 s.33
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• pp.1-5
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• 2004

A multi-layer flexible substrate is composed of copper(Cu)/polyimide that are known as good electrical conductivity, and low dielectric constant, respectively. In this study. conductor line of $5{\mu}m$-pitch was successfully fabricated without non-uniform pattern shape by electroplating copper and coating polyimide on patterned stainless steel. For multi-layer flexible substrate, via holes were drilled by UV laser and filled with electroplating copper and tin. And then, the PI layer with vias and conductor lines was stripped from stainless steel substrate. The PI layers were laminated at once with careful alignment between layers. Solid state reaction between tin and copper during lamination formed the intermetallic compounds of $Cu_6Sn_5$($\eta$-phase) and $Cu_3Sn$($\epsilon$-Phase) and achieved a complete inter-connection by vertically positioning the plugged via holes on via pad. The via formation process has several advantages; such as better electrical property and lower cost than V type via and paste via.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.3
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• pp.206-210
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• 2010

$BaTiO_3$ dielectric ceramics are widely used to multi-layer ceramic capacitor. The $BaTiO_3$ powder was synthesized at $950^{\circ}C$ by using a solid state reaction and grinded by using a high-energy mill. And then, 2.53 wt% glass frit was added to the synthesized $BaTiO_3$ powders for lowering the sintering temperature. The mixed powders were sintered at various temperatures of $1170^{\circ}C$, $1200^{\circ}C$, $1230^{\circ}C$. Microstructures of the sintered $BaTiO_3$ ceramics were inspected by SEM and crystal structures were analyzed by XRD method. The relative dielectric constant was measured by using a impedance/gain phase analyzer. The synthesized $BaTiO_3$ powder had the tetragonal perovskite structure without secondary phase and the particle size was below 200 nm. The relative densities measured at the samples sintered at the temperature above $1200^{\circ}C$ were about 95%. The relative dielectric constant showed maximum value of 2310, which was measured in the specimen sintered at $1200^{\circ}C$. From these results, we could know that the added glass frit had effects on both lowering the sintering temperature and improving the dielectric property.

• Journal of Advanced Navigation Technology
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• v.17 no.6
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• pp.720-725
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• 2013

This paper has presented that fringing-electric fields enhanced by a finger-type electrode can improve the tunability of the tunable capacitor. Its top electrodes with different area and line width are designed in types of the finger for a long conducting perimeter. The tunable varactors were fabricated on a quartz substrate employing a multi-layer dielectric of a para/ferro/para-electric thin film. Compared to the conventional capacitor, finger-type capacitors are analyzed in terms of effective capacitance and tunablility. Their effective capacitance and tunability of the varactors with the long perimeter increase 24~40 % and 7~12 %, respectively, due to enhanced fringing electric fields from 1 to 2.5 GHz.