• 전기전자학회논문지
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• 제26권4호
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• pp.714-721
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• 2022

다중 주파수 클럭 신호를 사용하는 시스템 온 칩(SoC: system on a chip)를 위해 위상 고정 루프(PLL: phase-locked loop) 기반 주파수 합성기가 제안된다. 제안하는 PLL 기반 주파수 합성기는 위상 주파수 검출기(PFD: phase frequency detector), 전하 펌프(CP: charge pump), 루프 필터, 전압 제어 발진기(VCO: voltage-controlled oscillator), 그리고 주파수 분주기로 구현되는 전하 펌프 위상 고정 루프와 에지 컴바이너로 구성된다. PLL은 6개의 차동 지연 셀을 사용하여 VCO에 의해 12 위상 클록을 출력하며, 에지 컴바이너는 PLL의 12상 출력 클럭의 에지 컴바이닝과 주파수 분주를 통해 출력 클럭의 주파수를 합성한다. 제안된 PLL 기반 주파수 합성기는 1.2V 공급전압을 사용하는 55nm CMOS 공정에서 설계된다. 설계된 PLL 기반 주파수 합성기는 주파수가 20.75MHz인 기준 클록에 대해 166MHz, 83MHz 및 124.5MHz의 세 클록 신호를 출력한다.

• 한국음향학회지
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• 제20권8호
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• pp.19-23
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• 2001

고속 저전력의 DSP (Programmable Digital Signal Processor)가 개발됨에 따라 이동통신 분야에서 시스템 및 단말기 등이 DSP를 사용하여 구현되고 있다. 본 논문에서는 DSP를 사용한 AMR (Adaptive Multi-rate) 음성부호화기의 멀티 채널 실시간 구현에 관하여 논한다. AMR 음성부호화 알고리즘을 250 MHz로 동작하는 32비트 정수형 DSP 칩인 TMS320C6202를 사용하여 구현하였다. 실시간 동작을 위하여 cross compile, 선형 어셈블리 최적화, TMS320C62xx 어셈블리 최적화 작업을 수행하였다. AMR 음성부호화기에 음성 데이터 입출력 기능 및 외부 CPU와의 통신기능을 포함하였다. DSP EVM 보드를 사용하여 AMR 음성부호화기를 개발하였고, ETRI에서 개발중인 비동기 IMT-2000 시스템 상에서 동작 및 기능을 검증하였다.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2005년도 하계학술대회
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• pp.427-430
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• 2005

A multi-code biorthogonal code keying (MBCK) system consists of multiple waveform coding blocks, and the sum of output codewords is transmitted. Drawback of MBCK is that it requires amplifier with high linearity because its output symbol is multi-level. MBCK with constant amplitude precoding block (CA-MBCK) has been proposed, which guarantees sum of orthogonal codes to have constant amplitude. The precoding block in CA-MBCK is a redundant waveform coder whose input bits are generated by processing the information bits. Redundant bits of constant amplitude coded CA-MBCK are not only used to make constant amplitude signal but also used to improve the BER performance at the receiver. In this paper, we proposed a transmission scheme which combines CA-MBCK with $Q^2PSK$ modulation to improve bandwidth efficiency of CA-MBCK and also uses chip interleaving to maintain a constant amplitude feature of CA-MBCK. bandwidth efficiency of a proposed transmission scheme is increased fourfold. And the BER performance of the scheme is same as that of CA-MBCK.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2005년도 춘계학술대회논문집
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• pp.319-324
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• 2005

The interface between host processor and the ShortStack Micro Server may be a Serial Communication Interface(SCI). The LonWorks control module with a high performance is developed, which is composed of the 8 bit PIC Microprocessor for host processor and the smart neuron chip for the ShoretStack Micro Server. This intelligent control board is verified as proceeding the various function tests from experimental system with an boost pump and inverter driving systems. It is also confirmed that the developed control module provides stably 0-10VDC linear signal to the input signal of inverter driving system for varying the induction motor speed. Thus, the experimental results show that the fabricating intelligent board carried out very well the various functions in the wide operating ranges of boost pump system. This developed control module expect to apply to industrial fields to require the comparatively exact control and monitoring such as multi-motor driving system with inverter, variable air volume system and the boost pump water supply systems.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권2호
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• pp.75-79
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• 2009

A system-on-a-chip communication architecture has a significant impact on the performance and power consumption of modern multi-processors system-on-chips (MPSoCs). However, customization of such architecture for a specific application requires the exploration of a large design space. Thus, system designers need tools to rapidly explore and evaluate communication architectures. In this paper we present the method for application-specific low-power bus architecture synthesis at system-level. Our paper has two contributions. First, we build a bus power model of AMBA AXI bus communication architecture. Second, we incorporate this power model into a low-power architecture exploration algorithm that enables system designers to rapidly explore the target bus architecture. The proposed exploration algorithm reduces power consumption by 20.1% compared to a maximally connected reduced matrix, and the area is also reduced by 20.2% compared to the maximally connected reduced matrix.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권3호
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• pp.207-220
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• 2011

Coarse-grained reconfigurable architecture (CGRA) based embedded systems aims to achieve high system performance with sufficient flexibility to map a variety of applications. However, the CGRA has been considered as prohibitive one due to its significant area/power overhead and performance bottleneck. In this work, I propose reconfigurable multi-array architecture to reduce power/area and enhance performance in configurable embedded systems. The CGRA-based embedded systems that consist of hierarchical configurable computing arrays with varying size and communication speed were examined for multimedia and other applications. Experimental results show that the proposed approach reduces on-chip area by 22%, execution time by up to 72% and reduces power consumption by up to 55% when compared with the conventional CGRA-based architectures.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.102.2-102
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• 2001

In this study, a solid-state laser system adopting a new real time multi-discharge (RTMD) method in which three flashlamps are turned on consecutively was designed and fabricated to examine the pulse width and the pulse shape of the laser beams depending upon the changes in the lamp turn-on time. That is, this study shows a technology that makes it possible to make various pulse shapes by turning on three flashlamps consecutively on a real-time basis with the aid of a PIC one-chip microprocessor, With this technique, the lamp turn-on delay time can be varied more diversely from 0 to 10 ms and the real-time control is possible with an external keyboard, enabling various pulse shapes. In addition, longer pulses can be more widely used for industrial processing and lots of medical purposes.

• Journal of electromagnetic engineering and science
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• 제4권2호
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• pp.56-62
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• 2004

We present a multi-Gbit/s digital I/O interface based on RF-modulation and capacitive-coupling over an impedance matched transmission line. The RF-interconnect(RFI) can greatly reduce the digital switching noise and eliminate the dc power dissipation over the channel. It also enables reduced signal amplitude(as low as 200 ㎷) with enhanced data rate and affordable circuit overhead. This paper addresses the system advantages and implementation issues of RFI. A prototype on-chip RFI transceiver is implemented in 0.18-${\mu}{\textrm}{m}$ CMOS. It demonstrates a maximum data rate of 2.2 Gbit/s via 10.5-㎓ RF-modulation. The RFI can be very instrumental for future high-speed inter- and intra-ULSI data links.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 전력전자학술대회 논문집
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• pp.308-311
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• 2001

Most of the battery charger for electric powered forklift truck are controlled by the method of 3-phased constant current and constant voltage. However, these chargers have several disadvantages like a large charger capacity, and a short battery life time. This paper presents a digital type battery charger based on multi-mode control adding a constant power control and several assistant controls in the conventional control. The whole control system is performed by a low cost one-chip micro-controller and completely digitize. So we can get a high precision control and a good reliability.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 하계학술대회 논문집 C
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• pp.1852-1854
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• 2003

In manufacturing processes, various and suitable pulse shapes are required for the purpose of material processing. In order to make various pulse shapes with variable pulse length and high duty cycle, We have fabricated the power supply consisting 6 SCRs and the Pulse Forming Network(PFN) with the precise delay time control. So our control system has three switching circuits, 3 mesh PFN, and simmer circuit. In addition, we have designed and fabricated the PIC one-chip microprocessor(16F877) to control the delay time of sequential switching.