• Title/Summary/Keyword: Multi-chip System

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Implementation of Co-Channel Radio Relay System and Its Performance Evaluation with Synchronous Digital Hierarchy (동기식 디지틀 계위의 동일채널 무선 전송장치구현 및 성능분석)

  • 서경환
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.35D no.11
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    • pp.10-22
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    • 1998
  • In this paper, as a way of improving the availability and spectral efficiency of radio relay system, a co-channel radio relay system based upon the synchronous digital hierarchy is developed and its performance measured by 64-QAM with a never-seen multi-purpose ASIC chip is illustrated. This system provides a couple of transmission capacity compared with alternative channel arrangement. By adopting a powerful complex 13-tap adaptive time domain equalizer and cross-pol interference canceller, improvement of more than 1.5 ~ 2.0 dB in signature is obtained in comparison to 9 or 11-tap adaptive time domain equalizer, and about 22.5 dB in improvement factor of cross-pol interference canceller is achieved at C/N of 24.5 dB. In addition, digital filter makes it possible to optimize the occupied bandwidth by selecting an appropriate roll-off factor externally. It is expected that co-channel radio relay system with the powerful multi-purpose ASIC chip plays a key role in creating a value-added product, reliability, and reducing the outage time.

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A Design and Fabrication of the Brick Transmit/Receive Module for K Band (K 대역 브릭형 능동 송수신 모듈의 설계 및 제작)

  • Lee, Ki-Won;Moon, Ju-Young;Yun, Sang-Won
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.19 no.8
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    • pp.940-945
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    • 2008
  • In this paper, we have designed the Brick Transmit/Receive Module for K-band which can be applied to active phase array radar system. The proposed structure of T/R Module for K band is brick type for MCM(Multi Chip Module) form and the satisfaction of tile type T/R Module can apply to structure of cavity and main characteristic. The fabricated brick type T/R Module confirmed the main characteristic for electrical goal performance in test and this structure can be applied to active phase array radar.

Design of A Low Power Memory Tag for Storing Emergency Manuals (긴급 매뉴얼 저장용 저전력 메모리 태그의 설계)

  • Kwak, Noh Sup;Eun, Seongbae;Son, Kyung A;Cha, Shin
    • Journal of Korea Multimedia Society
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    • v.23 no.2
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    • pp.293-300
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    • 2020
  • Since the communication networks like the Internet collapses at disaster and calamity sites, a maintenance system that can be operated offline is required for the maintenance of various facilities. In this paper, we propose a system that memory tags attached on the facilities may transmit the emergency manual to a smart-phone, and the smart phone displays it off-line. The main issue is to design low energy mode memory tags. This study presents two kinds of methods and analyzes each's energy consumption mode. The first one is to develop memory tags by using one chip, and the next one is to design memory tags by forming multi-modules. Both ways show proper application fields under the low energy mode. This research selects the off-line maintenance system by using one chip design, and proposes the direction of contents for enhancing the effectiveness of the system. And we expect that this memory tags will be valuable for disaster scenes as well as battle fields.

Low-Power Implementation of A Multichannel Hearing Aid Using A General-purpose DSP Chip (범용 DSP 칩을 이용한 다중 채널 보청기의 저전력 구현)

  • Kim, Bum-Jun;Byun, Joon;Park, Young-Cheol
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.11 no.1
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    • pp.18-25
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    • 2018
  • In this paper, we present a low-power implementation of the multi-channel hearing aid system using a general-purpose DSP chip. The system includes an acoustic amplification algorithm based on Wide Dynamic Range Compression (WDRC), an adaptive howling canceller, and a single-channel noise reduction algorithm. To achieve a low-power implementation, each algorithm is re-constructed in forms of integer program, and the integer program is converted to the assembly program using BelaSigna(R) 250 instructions. Through experiments using the implementation system, the performance of each processing algorithm was confirmed in real-time. Also, the clock of the implementation system was measured, and it was confirmed that the entire signal processing blocks can be performed in real time at about 7.02MHz system clock.

3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

  • Lee, Kang-Wook
    • Journal of the Microelectronics and Packaging Society
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    • v.22 no.2
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    • pp.11-19
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    • 2015
  • Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

Development of a General Purpose Motion Controller Using a Field Programmable Gate Array (FPGA를 이용한 범용 모션 컨트롤러의 개발)

  • Kim, Sung-Soo;Jung, Seul
    • Journal of Institute of Control, Robotics and Systems
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    • v.10 no.1
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    • pp.73-80
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    • 2004
  • We have developed a general purpose motion controller using an FPGA(Field Programmable Gate Array). The multi-PID controllers and GUI are implemented as a system-on-chip for multi-axis motion control. Comparing with the commercial motion controller LM 629, since it has multi-independent PID controllers, we have several advantages such as space effectiveness, low cost and lower power consumption. In order to test the performance of the proposed controller, motion of the robot hand is controlled. The robot hand has three fingers with 2 joints each. Finger movements show that tracking was very effective. Another experiment of balancing an inverted pendulum on a cart has been conducted to show the generality of the proposed FPGA PID controller. The controller has well maintained the balance of the pendulum.

A Study on Binary CDMA System Correlator Design for High-Speed Acquisition Processing (고속 동기 처리를 위한 Binary CDMA 시스템 코릴레이터 설계에 관한 연구)

  • Lee, Seon-Keun;Jeong, Woo-Yeol
    • Journal of the Korea Society of Computer and Information
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    • v.12 no.1 s.45
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    • pp.155-160
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    • 2007
  • Because output of multi-code CDMA system adapted high speed data transmission becoming multi-level system use linear amplifier in output stage and complex output signal. Therefore, Multi-Code CDMA system has shortcoming of high price, high complexity etc.. Binary CDMA technology that allow fetters in existing CDMA technology to supplement this shortcoming proposed. In binary CDMA system When correlator process high speed data, bottle-neck phenomenon is happened on synchronization acquisition process, it is very important parameter. Because existent correlator must there be advantage that power consumption is small but flow addition of several stages to receive correlation's value, the processing speed has disadvantage because the operation amount is much. Therefore in this paper, proposed correlator has characteristic such as data is able to high speed processing, chip area is independent and power consumption is constant in structure in binary CDMA system.

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고속 디지탈 퍼지 추론회로 개발과 산업용 프로그래머블 콘트롤러에의 응용

  • 최성국;김영준;박희재;고덕용;김재옥
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 1992.04a
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    • pp.354-358
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    • 1992
  • This paper describes a development of high speed fuzzy inference circuit for the industrialprocesses. The hardware fuzzy inference circuit is developed utilizing a hardware fuzzy inference circuit is developed utilizing a DSP and a multiplier and accumulator chip. To enhance the inference speed, the pipeline disign is adopted at the bottleneck and the general Max-Min inference method is slightly modified as Max-max method. As a results, the inference speed is evaluated to be 100 KFLIPS. Owing to this high speed feature, satisfactory application can be attained for complex high speed motion control as well as the control of multi-input multi-output nonlinear system. As an application, the developed fuzzy inference circuit is embedded to a PLC (Porgrammable Logic Controller) for industrial process control. For the fuzzy PLC system, to fascilitate the design of the fuzzy control knowledge such as membership functions, rules, etc., a MS-Windows based GUI (Graphical User Interface) software is developed.

An Ameliorated Design Method of ML-AHB BusMatrix

  • Hwang, Soo-Yun;Jhang, Kyoung-Sun;Park, Hyeong-Jun;Bae, Young-Hwan;Cho, Han-Jin
    • ETRI Journal
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    • v.28 no.3
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    • pp.397-400
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    • 2006
  • The multi-layer advanced high-performance bus (ML-AHB) BusMatrix proposed by ARM is an excellent architecture for applying embedded systems with low power. However, there is one clock cycle delay for each master in the ML-AHB BusMatrix of the advanced microcontroller bus architecture (AMBA) design kit (ADK) whenever a master starts new transactions or changes the slave layers. In this letter, we propose an improved design method to remove the one clock cycle delay in the ML-AHB BusMatrix of an ADK. We also remarkably reduce the total area and power consumption of the ML-AHB BusMatrix of an ADK with the elimination of the heavy input stages.

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A DNA Microarray LIMS System for Integral Genomic Analysis of Multi-Platform Microarrays

  • Cho, Mi-Kyung;Kang, Jason Jong-ho;Park, Hyun-Seok
    • Genomics & Informatics
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    • v.5 no.2
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    • pp.83-87
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    • 2007
  • The analysis of DNA microarray data is a rapidly evolving area of bioinformatics, and various types of microarray are emerging as some of the most exciting technologies for use in biological and clinical research. In recent years, microarray technology has been utilized in various applications such as the profiling of mRNAs, assessment of DNA copy number, genotyping, and detection of methylated sequences. However, the analysis of these heterogeneous microarray platform experiments does not need to be performed separately. Rather, these platforms can be co-analyzed in combination, for cross-validation. There are a number of separate laboratory information management systems (LIMS) that individually address some of the needs for each platform. However, to our knowledge there are no unified LIMS systems capable of organizing all of the information regarding multi-platform microarray experiments, while additionally integrating this information with tools to perform the analysis. In order to address these requirements, we developed a web-based LIMS system that provides an integrated framework for storing and analyzing microarray information generated by the various platforms. This system enables an easy integration of modules that transform, analyze and/or visualize multi-platform microarray data.