• Title/Summary/Keyword: Multi-channel implementation

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Design and Implementation of a DSP-Based Multi-Channel Power Measurement System

  • Jeon Jeong-Chay;Oh Hun
    • KIEE International Transactions on Power Engineering
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    • v.5A no.3
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    • pp.214-220
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    • 2005
  • In order to improve energy efficiency and solve power disturbances, power components measurement for both the supply and demand side of a power system must be implemented before appropriate action on the power problems can be taken. This paper presents a DSP (Digital Signal Processor)-based multi-channel (voltage 8-channel and current 10-channel) power measurement system that can simultaneously measure and analyze power components for both supply and demand. Voltage 8-channel and current 10-channel measurement is made through voltage and current sensors connected to the developed system, and power components such as reactive power, power factor and harmonics are calculated and measured by the DSP. The measured data are stored in a personal computer (PC) and a commercial program is then used for measurement data analysis and display. After voltage and current measurement accuracy revision using YOKOGAWA 2558, the developed system was tested using a programmable ac power source. The test results showed the accuracy of the developed system to be about 0.3 percent. Also, a simultaneous measurement field test of the developed system was implemented by application to the supply and demand side of the three-phase power system.

Implementation of the Multi-Channel Network Controller using Buffer Sharing Mechanism (버퍼공유기법을 사용한 멀티채널 네트워크 컨트롤러 구현)

  • Lee, Tae-Su;Park, Jae-Hyun
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.56 no.4
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    • pp.784-789
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    • 2007
  • This paper presents an implementation of a new type of architecture to improve an overflow problem on the network buffer. Each receiver channel of network system stores the message in its own buffer. If some receiver channel receives many messages, buffer overflow problem may occur for the channel. This paper proposes a network controller that implements a receiver channel with shared-memory to save all of the received messages from the every incomming channels. The proposed architecture is applied to ARINC-429, a real-time control network for commercial avionics system. For verifying performance of the architecture, ARINC-429 controller is designed using a SOPC platform, designed by Verilog and targeted to Xilinx Virtex-4 with a built-in PPC405 core.

Low-Complexity Massive MIMO Detectors Based on Richardson Method

  • Kang, Byunggi;Yoon, Ji-Hwan;Park, Jongsun
    • ETRI Journal
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    • v.39 no.3
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    • pp.326-335
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    • 2017
  • In the uplink transmission of massive (or large-scale) multi-input multi-output (MIMO) systems, large dimensional signal detection and its hardware design are challenging issues owing to the high computational complexity. In this paper, we propose low-complexity hardware architectures of Richardson iterative method-based massive MIMO detectors. We present two types of massive MIMO detectors, directly mapped (type1) and reformulated (type2) Richardson iterative methods. In the proposed Richardson method (type2), the matrix-by-matrix multiplications are reformulated to matrix-vector multiplications, thus reducing the computational complexity from $O(U^2)$ to O(U). Both massive MIMO detectors are implemented using a 65 nm CMOS process and compared in terms of detection performance under different channel conditions (high-mobility and flat fading channels). The hardware implementation results confirm that the proposed type1 Richardson method-based detector demonstrates up to 50% power savings over the proposed type2 detector under a flat fading channel. The type2 detector indicates a 37% power savings compared to the type1 under a high-mobility channel.

Design and implementation of comb filter for multi-channel, 24bit delta-sigma ADC (다채널 24비트 델타시그마 ADC 용 콤필터 설계 및 구현)

  • Hong, Heedong;Park, Sangbong
    • The Journal of the Convergence on Culture Technology
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    • v.6 no.3
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    • pp.427-430
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    • 2020
  • The multi-channel analog signal to digital signal conversion is increasing in the field of IoT and medical measurement equipments. It has chip area and power consumption constraints to use a few single or 2_channel ADC for multi_channel application. This paper described to design and implement a proposed comb filter for multi-channel, 24bit ADC. The function of proposed comb filter is verified by matlab simulation and the FPGA test board. It was fabricated using SK Hynix 0.35㎛ CMOS standard process. The performance and chip size is compared with the existing design method that uses integrator/differentiator and FIR construction. The proposed comb filter is expected to use the IoT product and medical measurement equipments that require multi-channel, low power consumption and small hardware size.

Implementation of multi-channel active noise control systems for active barriers (능동방음벽을 위한 다중채널 능동소음제어 시스템의 구현)

  • Choi, Jung-Il;Cho, Hyun-Gi;Nam, Hyun-Do;Ahn, Dong-Jun
    • Proceedings of the KIEE Conference
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    • 2011.07a
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    • pp.2007-2008
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    • 2011
  • In this paper, we implemented active noise control systems for active barriers with attenuation of road noise. And then we constructed by multi-channel audio systems and DAQ part, high performance DSP H/W. Active noise control firmware program was implemented for multi-channel off-line/on-line estimation methods for secondary path transfer functions and FIR/IIR filter structure main noise control algorithms. To evaluate performance of implemented systems, active barriers test bed was implemented and several experiments was performed by various noise cases.

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Multi-Channel Authentication based Security Card Design and Implementation (다중 채널 인증 기반 보안 카드의 설계 및 구현)

  • Seo, Hwa-jeong;Kim, Ho-won
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.1
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    • pp.81-86
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    • 2016
  • In this paper, we present multi-channel authentication based security card design. Since this security card is written on the transparent paper, security information is extracted by overlaying the card with smartphone screen. This method removes the limitations of physical layout in previous security card and improves the security level. Furthermore, our security card is secure when our card is exposed to malicious users.

Design and Fabrication of multi-channel gas leakage monitoring system using CPLD (CPLD칩을 이용한 다채널 가스누출 경보시스템의 설계 및 제작)

  • 정도운;정완영;이덕동
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.925-928
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    • 1999
  • A multi-channel gas leakage monitoring system was designed and fabricated by using CPLD(complex Programmable Logic .Device) for monitoring and controlling the leakage of natural gas from supplying-pipes under the ground. Fabricated SnO$_2$thick film gas sensor elements were attached on safeguard steel plate of natural gas supplying pipes, and the local monitoring system in this study received the signal from the gas sensors. The monitoring system was implemented by using CPLD chip to reduce the development time and implement simple one chip system. The time division multi-channel system received the input signal from individual gas sensor at one of divided times by multiplexor and signal processed sequentially. The system reduced the size of peripheral circuit resulted in implementation of creditable simple system.

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A Fetal ECG Signal Monitoring System Using Digital Signal Processor (디지털 신호처리기를 사용한 태아심전도 신호 추출 시스템)

  • 박영철;조병모;김남현;김원기;박상휘;연대희
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.9
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    • pp.1444-1452
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    • 1989
  • This paper describes the implementation of a real time fetal ECG monitoring system in which an adaptive multi-channel noise canceller is realized using the Texas Instruments TMS32020 progrmmmable ditital signal processor. An ECG signal from the electrode placed on the mother's abdomen and three ECGs from those on the chest are applied as the desired signal and the referened inputs, respectively, of the multi-channel filter. The coefficients of the filter are updated using the LMS algorithm such that the output of the multi-channel filter copies the maternal ECG embedded in the abdominal ECG. The enhanced fetal ECG is obtained by subtracting the filter output from the abdominal ECG, and the difference signal is recorded. Both off-line and on-line experimental results are presented to verify the effectiveness of the parameters for the digital signal processing algorithms and the prototype system.

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A Study on Electronic Circuit for Liwe-Time Correction in Multi-Channel Analyzer : Survey and Analysis (방사선 스펙트럼 계측기 (Multi-Channel Analyzer)의 Live-Time 보상회로에 관한 연구)

  • Hwang, I.K.;Kwon, K.H.;Song, S.J.
    • Nuclear Engineering and Technology
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    • v.27 no.5
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    • pp.784-791
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    • 1995
  • This paper describes the counting-loss problem for radiation measurement Multi-channel analyzers and spectrometers adopt various techniques for compensation for counting-losses in process-ing the radiation pulses from a detector. Researchers hate tried to seek the best solution for the problem. However, any absolute solution has not been reached and vendors of radiation instruments use their own algorithms individually. This survey explains the various compensation algorithms with electronic implementation approach. Shortcomings and merits of each algorithm are also reviewed and a direction is suggested of the recommendable development strategy for counting-loss compensation.

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Real-time Implementation of Dolby Pro Logic Decoder Using ARM-7 Core (ARM-7 코어를 이용한 Dolby Pro Logic 복호기의 실시간 구현)

  • 이창우;이상근;조재문
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.8B
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    • pp.1412-1420
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    • 1999
  • In order to enhance multi-channel audio signals, Dolby Pro Logic is widely used especially for the Hi-Fi audio system, since it can provide highly stereophonic effects and a nice separation of multi-channel sound. This paper describes an implementation of Dolby Pro Logic decoder with ARM-7 core. The code is modified for the fixed point operation and optimized. For the verification of the code, the operation time and the precision are estimated thoroughly. As a result, it is verified that Dolby Pro Logic decoder can be implemented with ARM-7 core operating at 54 MHz.

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