• Proceedings of the Korean Society of Computer Information Conference
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• 2018.07a
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• pp.1-2
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• 2018

해상 선박의 안전을 위해 해저의 객체 및 장애물의 정확한 탐지를 위해 해저환경에서 감쇠현상이 비교적 적은 음파 기반의 소나가 널리 활용된다. 그러나 기존의 소나 영상 시뮬레이션은 고해상도의 영상, 잡음 처리, 해저지형과 객체 데이터 등의 방대한 데이터 처리로 인해 물체 탐지 및 식별을 위한 처리속도와 비용이 크게 증가한다. 이러한 문제를 최소화하기 위해서 해저지형, 객체 생성과 잡음 처리 모델을 Multi-Threading, SIMD 등 병렬처리를 적용하여 처리속도를 최적화 한다. 본 논문에서는 혼합된 병렬처리 방법을 적용하여 소나를 기반으로 해저 환경 시뮬레이션을 위한 모의 신호를 생성하는 성능을 향상시킨다. 병렬처리로 인해 개선된 성능을 순차처리에 따른 속도와 실험적으로 비교한다.

• Journal of Broadcast Engineering
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• v.22 no.4
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• pp.509-518
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• 2017

High-resolution digital holograms can be quickly generated by using a PC cluster that is based on server-client architecture and is composed of several GPU-equipped PCs. However, the data transmission time between PCs becomes a large obstacle for fast generation of video holograms because it linearly increases in proportion to the number of frames. To resolve the problem with the increase of data transmission time, this paper proposes a multi-threading-based method. Hologram generation in each client PC basically consists of three processes: acquisition of light sources, CGH operation using GPUs, and transmission of the result to the server PC. Unlike the previous method that sequentially executes the processes, the proposed method executes in parallel them by multi-threading and thus can significantly reduce the proportion of the data transmission time to the total hologram generation time. Through experiments, it was confirmed that the total generation time of a high-resolution video hologram with 150 frames can be reduced by about 30%.

• Journal of the Korea Society of Computer and Information
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• v.15 no.2
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• pp.155-162
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• 2010

To ensure accurate measurements of wireless network performance, it should be collected real-time data which are transmitted between a large number of nodes in the actual network environment. Therefore, it is necessary to develop simulation tool for finding optimal network system design method such as media access control, routing technique, ad-hoc algorithm of node deployment while overcoming spatial and temporal constraints. Our research attempts to provide an improved architecture and design method of simulation tool for wireless network is an application of multi-threading technique in these issues. We finally show that usability of the proposed simulator by comparing results derived from same test environment in the wireless LAN model of our simulator and widely used network simulation package, NS-2.

• Journal of Korea Society of Digital Industry and Information Management
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• v.12 no.1
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• pp.89-95
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• 2016

Recent growth of hacking threats and development in software and technology put Network security under threat, In addition, intrusion, malware and worm virus have been increased due to the existence of variety of sophisticated hacking methods. The goal of this study is to compare Snort Alpha version with Suricata 2.0.11 version whereas previous study focuses on comparison between snort 2. x version under thread environment and Suricata under multi-threading environment. This thesis' experiment environment is set as followed. Intel (R) Core (TM) i5-4690 3. 50GHz (4threads) of CPU, 16GB of RAM, 3TB of Seagate HDD, Ubuntu 14.04 are used. According to the result, Snort Alpha version is superior to Suricata in performance, but Snort Alpha had some glitches when executing pcap files which created core dump errors. Therefore this experiment seeks to analyze which performs better between Snort Alpha version that supports multi packet processing threads and Suricata that supports multi-threading. Through this experiment, one can expect the better performance of beta and formal version of Snort in the future.

• Journal of the Korean Society of Safety
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• v.39 no.1
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• pp.96-103
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• 2024

The demand for mass calculation of offsite consequence analysis to conduct exhaustive single-unit or multi-unit Level 3 PSA is increasing. In order to perform efficient offsite consequence analyses, the Korea Atomic Energy Research Institute is conducting model optimization studies to minimize the analysis time while maintaining the accuracy of the results. A previous study developed a model optimization method using efficient plume segmentation and verified its effectiveness. In this study, we investigated the possibility of optimizing the model through particle size distribution setting by checking the reduction in analysis time and deviation of the results. Our findings indicate that particle size distribution setting affects the results, but its effect on analysis time is insignificant. Therefore, it is advantageous to set the particle size distribution as fine as possible. Furthermore, we evaluated the effect of multithreading and confirmed its efficiency. Future optimization studies should be conducted on various input factors of offsite consequence analysis, such as spatial grid settings.

• The KIPS Transactions:PartA
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• v.13A no.2 s.99
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• pp.137-146
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• 2006

Shared Memory Multiprocessor (SMP) systems adopting Chip-level MultiThreading (CMT) technology are becoming mainstream servers in commercial applications and High Performance Computining (HPC) applications as well. OpenMP has become the standard paradigm to parallelize applications for SMP mostly because of its ease of use. As the demand for more computing power in HPC applications is growing rapidly, obtaining high performance and scalability for these applications parallelized using OpenMP API's will become more important. In this paper, we study the performance and scalability of HPC applications parallelized using OpenMP, SPEC OMPL (standard OpenMP benchmark suite), on the Sun Fire E25K server which adopts CMT technology. We also study the effect of CMT on SPEC OMPL.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.512-521
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• 2002

Recently, conventional superscalar RISC processors arrive their performance limit, and many researches on the next-generation architecture are concentrated on SMT(Simultaneous Multi-Threading). In SMT processors, multiple threads are executed simultaneously and share hardware resources dynamically. In this case, it is more important to supply instructions from multiple threads to processor core efficiently than ever. Because SMT architecture shows higher IPC(Instructions per cycle) than superscalar architecture, performance is influenced by fetch bandwidth and the size of fetch queue. Moreover, to use TLP(Thread Level Parallelism) efficiently, fetch thread selection algorithm and fetch bandwidth for each selected threads must be carefully designed. Thus, in this paper, the performance values influenced by these factors are analyzed. Based on the results, an optimal instruction fetch strategy for SMT processors is proposed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3A
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• pp.347-357
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• 2004

Network systems have been developed to meet the high performance of forwarding packets and flexibility for providing various services, so network processor emerged. In order to improve the performance of network processors, fast external interface and special functional units have been used. Recently as an architectural method of improving performance, the SMT(Simultaneous Multi Threading) architecture is proposed, but this architecture is difficult to implement due to its complexity. Therefore research for architectural optimization is needed to develop the SMT network processors. In this paper we analyze each functional units on performing network algorithms and propose an optimized SMT network Processor architecture.

• The KIPS Transactions:PartA
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• v.17A no.2
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• pp.73-80
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• 2010

As the power of hardware has improved, there have been numerous researches in processing concurrently using multitasking method. The incremental evaluation is the evaluation method of reevaluating only affected parts instead of reevaluating overall program when the program has been changed. It is necessary to do more studies that improve the efficiency of concurrent incremental evaluation to do multitasking using multi-threading of Java not to do in parallel using multiprocessor. In this paper, the dependency in the dependency chart is based on the attribute that describes the real value of the variable that directly affects the semantics, thereby doing efficient evaluation. So using the dependency, this paper presents the concurrent incremental evaluation algorithm for Java Languages and proves its correctness, analyzing the efficiency of concurrent incremental evaluation by the simulation.

• Proceedings of the IEEK Conference
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• 2003.07d
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• pp.1387-1390
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• 2003

The superscalar architecture shows limit in performance improvement recently. While, SMT(Simultaneous Multi-Threading) architecture is receiving remark. The purpose of SMT architecture is to improve the performance of superscalar microprocessors by executing multi threads at the same time. In this paper, a load/store unit(LSU) suitable for ARM-compatible SMT microprocessors is presented. This LSU supports load instructions and store instructions of ARM ISA. This LSU keeps away the degradation of SMT by cache miss.