• The Transactions of the Korean Institute of Electrical Engineers A
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• v.55 no.6
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• pp.242-248
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• 2006

This paper proposes a coordinated control method for under-load tap changers (ULTCs) with shunt capacitors to reduce the operation numbers of both devices. The proposed method consists of two stages. In the first stage, the dispatch schedule is determined using a genetic algorithm with forecasted loads to reduce the power loss and to improve the voltage profile during a day. In the second stage, each capacitor operates according to this dispatch schedule and the ULTCs are controlled in real time with the modified reference voltages considering the dispatch schedule of the capacitors. The performance of the method is evaluated for the modified IEEE 14-bus system. Simulation results show that the proposed method performs better than a conventional control method.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.4
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• pp.321-328
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• 2008

In this paper, variable gain amplifier(VGA) with a gain slope controller has been proposed and verified by circuit simulations and measurements. The proposed VGA has a gain control, gain slope switch and variable gain range. The input source coupled pair with diode connected load is used for VGA gain stage. The gain slope controller with switch can control VGA gain slope. The proposed VGA is fabricated in $0.18{\mu}m$ CMOS process for multi -standard wireless receiver. The proposed two stage VGA consumes min. 2.0 mW to max. 2.6 mW in gain control range and gives input IP3 of -3.77 dBm and NF of 28.7 dB at 1.8 V power supply under -25 dBm, 1 MHz input. The proposed VGA has 37 dB(-16 dB $\sim$ 21 dB) variable gain range, and 8 dB gain range control per 0.3 V control voltage, and can provide variable gain, positive and negative gain slope control, and gain range control. This VGA characteristics provide design flexibility in multi-standard wireless receiver.

• Journal of Electrical Engineering and Technology
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• v.2 no.2
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• pp.152-156
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• 2007

This paper proposes a method for real-time control of both capacitors and ULTC in a distribution system to reduce the total power loss and to improve the voltage profile over the course of a day. The multi-stage consists of the off-line stage to determine dispatch schedule based on a load forecast and the on-line stage generates the time and control sequences at each sampling time. It is then determined whether one of the control actions in the control sequence is performed at the present sampling time. The proposed method is presented for a typical radial distribution system with a single ULTC and capacitors.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1318-1328
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• 2015

The photovoltaic (PV) power conditioning system for small-scale applications has gained significant interest in the past few decades. However, the standalone mode of operation has been rarely approached. This paper presents a two-stage multi-level micro-inverter topology that considers the different operation modes. A multi-output flyback converter provides both the DC-Link voltage balancing for the multi-level inverter side and maximum power point tracking control in grid connection mode in the PV stage. A modified H-bridge multi-level inverter topology is included for the AC output stage. The multi-level inverter lowers the total harmonic distortion and overall ratings of the power semiconductor switches. The proposed micro-inverter topology can help to decrease the size and cost of the PV system. Transient analysis and controller design of this micro-inverter have been proposed for stand-alone and grid-connected modes. Finally, the system performance was verified using a 120 W hardware prototype.

• Journal of Satellite, Information and Communications
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• v.7 no.2
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• pp.76-79
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• 2012

Satellite power system is critical for mission design and survival operation. Accordingly power conversion circuit has to stable design and verify for operation condition change (load, voltage, thermal condition). however, multi-stage make complicate for modeling and get all state solution. In this paper present all state solution for multi-stage converter by using Extended Describing Function(EDF) modelling. EDF modelling has merit to solve complex circuit but it has limit too. Because of fundamental approximation, EDF modeling is not match all topology. Consequently, we verify passible topology for EDF modeling and stable design multi-stage converter.

• Proceedings of the KIEE Conference
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• 1999.11d
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• pp.1160-1163
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• 1999

In this study, we developed FE-tip lithography system that could apply to multi-tip system and did lithography using FE-tip. The software that control FE-tip lithography system, was proposed for acquiring more adaptive data to compensate the effect of fluctuation. We found that the fluctuation effect was reduced. The minimum line width was related to applied voltage and we observed a movement of Z-axis piezo stage to correct the error of this system. When FE current was 5nA, scanning speed was $3{\mu}m/sec$ and applied voltage was 200V, we made a line pattern which had minimum line width of 614 nm. If we reduce applied voltage to several decades and increase scanning speed to $20{\mu}m/sec$, it is possible to set the minimum line width of 100 nm. The proposed system can be easily applied to multi FE-tip lithography system.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.535-540
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• 1998

This paper discusses a triple stage current source GTO inverter system for high power motor drives. The energy rebound circuit of the triple stage inverter not only controls the spike voltage of the GTO inverter but also facilitates PWM control of the thyristor rectifier operated at unity fundamental input power factor. Based on Pspice simulation and experiments, the principles and PWM pulse pattern for removing specific lower harmonics in the inverter's output current are discussed in detail.

• Journal of Power Electronics
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• v.2 no.4
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• pp.312-324
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• 2002

This paper presents a new PWM DC/DC converter with dual output power using single power stage, which has the isolation characteristics between each dual output. The proposed converter topology consists of two switches ($S_B$ and $S_F$) and only single secondary winding. Therefore, the proposed converter has better advantages of not only low cost and small size but also high power density because of using minimum components and devices compared with conventional methods which use multi winding transformers or several converters. The operating principle of the proposed converter topology, which includes the conventional auxiliary ZVT (Zero-Voltage-Transition) circuit to implement soft switching of the main switch, is illustrated in detail and the validity of the proposed converter is verified through several simulated and experimental results.

• ETRI Journal
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• v.37 no.6
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• pp.1188-1198
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• 2015

In this paper, a multi-time programmable (MTP) cell based on a $0.18{\mu}m$ bipolar-CMOS-DMOS backbone process that can be written into by using dual pumping voltages - VPP (boosted voltage) and VNN (negative voltage) - is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p-wells are used - one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n-well is used for the 256-bit MTP cell array. In addition, a three-stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of $1row{\times}64columns$ and a user memory area of $3rows{\times}64columns$, is newly proposed in this paper.

• Journal of Power Electronics
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• v.18 no.3
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• pp.694-701
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• 2018

This paper proposes a new single-phase power converter topology for changing the frequency of AC voltage. The proposed single-phase frequency converter (SFC) includes a T-type multi-level power converter (TMPC), a frequency decoupling transformer (FDT) and a digital signal processor (DSP). The TMPC can convert a 60 Hz AC voltage to a DC voltage and then convert the DC voltage to a 50 Hz AC voltage. Therefore, the output currents of the two T-type power switch arms have 50 Hz and 60 Hz components. The FDT is used to decouple the 50 Hz and 60 Hz components. The salient feature of the proposed SFC is that only one power electronic converter stage is used since the functions of the AC-DC and DC-AC power conversions are integrated into the TMPC. Therefore, the proposed SFC can simplify both the power circuit and the control circuit. In order to verify the functions of the proposed SFC, a hardware prototype is established. Experimental results verify that the performance of the proposed SFC is as expected.