• ETRI Journal
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• v.27 no.1
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• pp.81-88
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• 2005

In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 ${\mu}m$ dual gate oxide CMOS technology.

• Proceedings of the KSME Conference
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• 2003.04a
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• pp.1441-1446
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• 2003

The design optimization of the plate heat exchanger with staggered pin arrays for a fixed volume is performed numerically. The flow and thermal fields are assumed to be a streamwise-periodic flow and heat transfer with constant wall temperature and they are solved by using the finite volume method. The optimization is carried out by using the sequential linear programming (SLP) method and the weighting method is used for solving the multi-objective problem. The results show that the optimal design variables for the weighting coefficient of 0.5 are as follows; S=6.497mm, P=5.496mm, $D_1=0.689mm$, and $D_2=2.396mm$. The Pareto optimal solutions are also presented.

• Nuclear Engineering and Technology
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• v.42 no.5
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• pp.500-519
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• 2010

AEGIS is a lattice physics code incorporating the latest advances in lattice physics computation, innovative calculation models and efficient numerical algorithms and is mainly used for light water reactor analyses. Though the primary objective of the AEGIS code is the preparation of a cross section set for SCOPE2 that is a three-dimensional pin-by-pin core analysis code, the AEGIS code can handle not only a fuel assembly but also multi-assemblies and a whole core geometry in two-dimensional geometry. The present paper summarizes the major calculation models and part of the verification/validation efforts related to the AEGIS code.

• Nuclear Engineering and Technology
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• v.53 no.10
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• pp.3207-3216
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• 2021

Three-dimensional structures of a vortical flow field and heat transfer characteristics in a partially blocked 7-pin fuel assembly mock-up of sodium-cooled fast reactor have been investigated through a numerical analysis using a commercial computational fluid dynamics code, ANSYS CFX. The simulation with the SST turbulence model agrees well with the experimental data of outlet and cladding wall temperatures. From the analysis on the limiting streamline at the wall, multi-scale vortexes developed in axial direction were found around the blockage. The vortex core has a high cladding wall temperature, and the attachment line has a low cladding wall temperature. The small-scale vortex structures significantly enhance the convective heat transfer because it increases the turbulent mixing and the turbulence kinetic energy. The large-scale vortex structures supply thermal energy near the heated cladding wall surface. It is expected that control of the vortex structures in the fuel assembly plays a significant role in the convective heat transfer enhancement. Furthermore, the blockage plate and grid spacer increase the pressure drop to about 36% compared to the bare case.

• Korean Journal of Optics and Photonics
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• v.25 no.1
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• pp.21-28
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• 2014

In this paper a Super Multi-view display method using a pinhole array with full parallax was proposed. The proposed method was simulated and its parameters analyzed. Also, the distribution and irradiance of light through each pinhole on the retina receiver, according to the change of crystalline lens focal length, were found by simulation. As a result, an image free of blurring was obtained while the crystalline lens focused on the depth plane of the three-dimensional image created by the imaging lens.

• Nuclear Engineering and Technology
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• v.34 no.3
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• pp.250-258
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• 2002

This Paper is to apply the well-established coarse mesh finite difference(CMFD) method to the method of characteristics(MOC) transport calculation as an acceleration scheme. The CMFD problem is first formulated at the pin-cell level with the multi-group structure To solve the cell- based multi-group CMFD problem efficiently, a two-group CMFD formulation is also derived from the multi-group CMFD formulation. The performance of the CMFD acceleration is examined for three test problems with different sizes including a realistic quarter core PWR problem. The CMFD formulation provides a significant reduction in the number of ray tracings and thus only about 9 ray tracing iterations are enough for the realistic problem. In computing time, the CMFD accelerated case is about two or three times faster than the coarse-mesh rebalancing(CMR) accelerated case.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.3-17
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• 2003

.Package Trend -> Memory : Lighter, Thinner, Smaller & High Density => SiP, 3D Stack -> MPU : High Pin Counts & Multi-functional => FCBGA .Interposer Trend -> Via - Unfilled Via => Filled Via - Staggered Via => Stacked Via -> Emergence of All-layer Build-up Processes -> Interposer Material Requirement => Low CTE, Low $D_{k}$, Low $D_{f}$, Halogen-free .New Technology Concept -> Embedded Passives, Imprint, MLTS, BBUL etc.

• Transactions of Materials Processing
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• v.18 no.2
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• pp.122-127
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• 2009

The injection mold with multi-cavity is essential for mass production of plastic products. Multi-cavity molds are designed to geometrically balanced runner system to uniformly fill to each cavity. However, despite geometrical balanced runner system, filling imbalances between cavity to cavity have always been observed in injection molding. To solve these problems, many studies such as Melt Flipper, RC Pin, and others have been presented. The results of these studies have been an effect on filling balances in multi-cavity molds. But, those have had a limitation that additional insert parts must have existed in the mold. In this study, a new runner system is suggested for filling balance between cavity to cavity using "Melt-Buffer" with simple change of runner shape. A series of simulation to confirm feasibility of Melt-Buffer's effects was conducted using injection molding CAE program. Also, a series of injection molding experiment was conducted using plastic materials such as ABS and PP. As results of this study, feasibilities of filling balances by Melt-Buffer were confirmed.

• Proceedings of the Korean Society of Agricultural Engineers Conference
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• 2001.10a
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• pp.271-274
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• 2001

Experiments on the yield strength of pipe connectors made of metal wire, joint pins, pole pipes, multi span insertion joints, and T-clamp joints used in pipe houses were conducted. The strength of connections of a pipe connector made of metal wire was adequate but it had a big difference according to loading direction. The collapse load of pipes connected with a joint pin was lower than that of single pipes. Also experimental results showed that pole pipes for use in a part of frame buried under the ground were safe, and the strength of multi span insertion joints should be increased. The resistant moment of T-clamp was about 13.7% of a single pipe.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.823-826
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• 2003

FPGA-based logic emulator with lane gate capacity generally comprises a large number of FPGAs connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multi-FPGA system incorporating several state-of-the-art FPGAs. This paper proposes a circuit partitioning algorithm called SCATOMi(SCheduling driven Algorithm for TOMi)for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(Time-multiplexed, Off-chip, Multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Architecture comparison show that the pin count is reduced to 15.2%-81.3% while the critical path delay is reduced to 46.1%-67.6% compared to traditional architectures.