• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.736-744
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• 2016

Network on chip (NoC) is an emerging technology in the field of multi core interconnection architecture. The routers plays an essential components of Network on chip and responsible for packet delivery by selecting shortest path between source and destination. State-of-the-art NoC designs used routing table to find the shortest path and supports four ports for packet transfer, which consume high power consumption and degrades the system performance. In this paper, the multi port multi core router architecture is proposed to reduce the power consumption and increasing the throughput of the system. The shared buffer is employed between the multi ports of the router architecture. The performance of the proposed router is analyzed in terms of power and current consumption with conventional methods. The proposed system uses Modelsim software for simulation purposes and Xilinx Project Navigator for synthesis purposes. The proposed architecture consumes 31 mW on CPLD XC2C64A processor.

• Steel and Composite Structures
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• v.21 no.3
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• pp.605-628
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• 2016

The energy absorption characteristics of diamond core sandwich cylindrical columns under axial crushing process depend greatly on the amount of material which participates in the plastic deformation. Both the single-objective and multi-objective optimizations are performed for columns under axial crushing load with core thickness and helix pitch of the honeycomb core as design variables. Models are optimized by multi-objective particle swarm optimization (MOPSO) algorithm to achieve maximum specific energy absorption (SEA) capacity and minimum peak crushing force (PCF). Results show that optimization improves the energy absorption characteristics with constrained and unconstrained peak crashing load. Also, it is concluded that the aluminum tube has a better energy absorption capability rather than steel tube at a certain peak crushing force. The results justify that the interaction effects between the honeycomb and column walls greatly improve the energy absorption efficiency. A ranking technique for order preference (TOPSIS) is then used to sort the non-dominated solutions by the preference of decision makers. That is, a multi-criteria decision which consists of MOPSO and TOPSIS is presented to find out a compromise solution for decision makers. Furthermore, local and global sensitivity analyses are performed to assess the effect of design variable values on the SEA and PCF functions in design domain. Based on the sensitivity analysis results, it is concluded that for both models, the helix pitch of the honeycomb core has greater effect on the sensitivity of SEA, while, the core thickness has greater effect on the sensitivity of PCF.

• Nuclear Engineering and Technology
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• v.53 no.3
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• pp.851-859
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• 2021

Small PWR can be used for power generation and heating. Considering that small PWR has the characteristics of flexible operating conditions and complex operating environment, the controller designed based on single power level is difficult to achieve the ideal control of small PWR in the whole range of core power range. To solve this problem, a flexible switching controller based on fuzzy controller and LQG/LTR controller is designed. Firstly, a core fuzzy multi-model suitable for full power range is established. Then, T-S fuzzy rules are designed to realize the flexible switching between fuzzy controller and LQG/LTR controller. Finally, based on the core power feedback principle, the core flexible switching control system of small PWR is established and simulated. The results show that the flexible switching controller can effectively control the core power of small PWR and the control effect has the advantages of both fuzzy controller and LQG/LTR controller.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.8
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• pp.863-867
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• 2010

Multi-core processors are becoming increasingly popular. As they are widely adopted in embedded systems as well as desktop PC's, many multimedia applications are being parallelized on multi-core platforms. However, it is difficult to parallelize applications with inherent data dependencies such as encryption algorithms for multimedia data. In order to overcome this limit, we propose a technique to overlap computation and communication using an otherwise idle core in this paper. In particular, we interpret the problem of multimedia computation and communication as a pipeline design problem at the application program level, and derive an optimal number of stages in the pipeline.

• Journal of Computing Science and Engineering
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• v.5 no.2
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• pp.131-140
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• 2011

Different cores typically share the last-level cache in a multi-core processor. Threads running on different cores may interfere with each other. Therefore, the multi-core worst-case execution time (WCET) analyzer must be able to safely and accurately estimate the worst-case inter-thread cache interference. This is not supported by current WCET analysis techniques that manly focus on single thread analysis. This paper presents a novel approach to analyze the worst-case cache interference and bounding the WCET for threads running on multi-core processors with shared L2 instruction caches. We propose to use an interference matrix to model inter-thread interference, on which basis we can calculate the worst-case inter-thread cache interference. Our experiments indicate that the proposed approach can give a worst-case bound less than 1%, as in benchmark fib-call, and an average 16.4% overestimate for threads running on a dual-core processor with shared-L2 cache. Our approach dramatically improves the accuracy of WCET overestimatation by on average 20.0% compared to work.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.1
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• pp.1-10
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• 2017

Recently, with the ever-increasing complexity of industrial robot systems, it has been greatly attention to adopt a multi-core based motion controller with high cost-performance ratio. In this paper, we propose a software architecture that aims to utilize the computing power of multi-core processors. The key concept of our architecture is to use shared memory for the interplay between threads running on separate processor cores. And then, we have integrated our proposed architecture with an industrial standard compliant IDE for automatic code generation of motion runtime. For the performance evaluation, we constructed a test-bed consisting of a motion controller with Preempt-RT Linux based dual-core industrial PC and a 3-axis industrial robot platform. The experimental results show that the actuation time difference between axes is 10 ns in average and bounded up to 689 ns under $1000{\mu}s$ control period, which can come up with real-time performance for industrial robot.

• Journal of Information Processing Systems
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• v.14 no.2
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• pp.499-509
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• 2018

Recently, hybrid transactional memory (HyTM) has gained much interest from researchers because it combines the advantages of hardware transactional memory (HTM) and software transactional memory (STM). To provide the concurrency control of transactions, the existing HyTM-based studies use a bloom filter. However, they fail to overcome the typical false positive errors of a bloom filter. Though the existing studies use a global lock, the efficiency of global lock-based memory allocation is significantly low in multi-core environment. In this paper, we propose an efficient hybrid transactional memory scheme using near-optimal retry computation and sophisticated memory management in order to efficiently process transactions in multi-core environment. First, we propose a near-optimal retry computation algorithm that provides an efficient HTM configuration using machine learning algorithms, according to the characteristic of a given workload. Second, we provide an efficient concurrency control for transactions in different environments by using a sophisticated bloom filter. Third, we propose a memory management scheme being optimized for the CPU cache line, in order to provide a fast transaction processing. Finally, it is shown from our performance evaluation that our HyTM scheme achieves up to 2.5 times better performance by using the Stanford transactional applications for multi-processing (STAMP) benchmarks than the state-of-the-art algorithms.

• IEMEK Journal of Embedded Systems and Applications
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• v.17 no.6
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• pp.375-382
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• 2022

This paper proposes a multi-core cooperative computing structure considering the heterogeneous features of automotive embedded on-chip software. The automotive embedded software has the heterogeneous execution flow properties for various hardware drives. Software developed with a homogeneous execution flow without considering these properties will incur inefficient overhead due to core latency and load. The proposed method was evaluated on an target board on which a automotive MCU (micro-controller unit) with built-in multi-cores was mounted. We demonstrate an overhead reduction when software including common embedded system tasks, such as ADC sampling, DSP operations, and communication interfaces, are implemented in a heterogeneous execution flow. When we used the proposed method, embedded software was able to take advantage of idle states that occur between heterogeneous tasks to make efficient use of the resources on the board. As a result of the experiments, the power consumption of the board decreased by 42.11% compared to the baseline. Furthermore, the time required to process the same amount of sampling data was reduced by 27.09%. Experimental results validate the efficiency of the proposed multi-core cooperative heterogeneous embedded software execution technique.

• Journal of the Korean Society of Safety
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• v.35 no.1
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• pp.97-106
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• 2020

The objective of this paper is to suggest a new quantification method for multi-unit probabilistic safety assessment (PSA) that removes the overestimation error caused by the existing delete-term approximation (DTA) based quantification method. So far, for the actual plant PSA model quantification, a fault tree with negates have been solved by the DTA method. It is well known that the DTA method induces overestimated core damage frequency (CDF) of nuclear power plant (NPP). If a PSA fault tree has negates and non-rare events, the overestimation in CDF drastically increases. Since multi-unit seismic PSA model has plant level negates and many non-rare events in the fault tree, it should be very carefully quantified in order to avoid CDF overestimation. Multi-unit PSA fault tree has normal gates and negates that represent each NPP status. The NPP status means core damage or non-core damage state of individual NPPs. The non-core damage state of a NPP is modeled in the fault tree by using a negate (a NOT gate). Authors reviewed and compared (1) quantification methods that generate exact or approximate Boolean solutions from a fault tree, (2) DTA method generating approximate Boolean solution by solving negates in a fault tree, and (3) probability calculation methods from the Boolean solutions generated by exact quantification methods or DTA method. Based on the review and comparison, a new intersection removal by probability (IRBP) method is suggested in this study for the multi-unit PSA. If the IRBP method is adopted, multi-unit PSA fault tree can be quantified without the overestimation error that is caused by the direct application of DTA method. That is, the extremely overestimated CDF can be avoided and accurate CDF can be calculated by using the IRBP method. The accuracy of the IRBP method was validated by simple multi-unit PSA models. The necessity of the IRBP method was demonstrated by the actual plant multi-unit seismic PSA models.

• The Bulletin of The Korean Astronomical Society
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• v.40 no.1
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• pp.53.2-53.2
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• 2015

Fiber Bragg gratings (FBGs) are the most compact and reliable method of suppressing atmospheric emission lines in the infrared for ground-based telescopes. It has been proved that real FBGs based filters were able to eliminate 63 bright sky lines with minimal interline losses in 2011 (GNOSIS). Inscribing FBGs on multi-core fibers offers advantages. Compared to arrays of individual SMFs, the multi-core fiber Bragg grating (MCFBG) is greatly reduced in size, resistant to damage, simple to fabricate, and easy to taper into a photonics lantern (PRAXIS). Multi-mode fibers should be used and the number of modes has to be large enough to capture a sufficient amount of light from the telescope. However, the fiber Bragg gratings can only be inscribed in the single-mode fiber. A photonic lantern bi-directionally converts multi-mode to single-mode. The number of cores in MCFBGs corresponds to the mode. For a writing system consisting of a single ultra-violet (UV) laser and phase mask, the standard writing method is insufficient to produce uniform MCFBGs due to the spatial variations of the field at each core within the fiber. Most significant technical challenges are consequences of the side-on illumination of the fiber. Firstly, the fiber cladding acts as a cylindrical lens, narrowing the incident beam as it passes through the air-cladding interface. Consequently, cores receive reduced or zero illumination, while the focusing induces variations in the power at those that are exposed. The second effect is the shadowing of the furthest cores by the cores nearest to the light source. Due to a higher refractive index of cores than the cladding, diffraction occurs at each core-cladding interface as well as cores absorb the light. As a result, any core that is located directly behind another in the beam path is underexposed or exposed to a distorted interference pattern from what phase mask originally generates. Technologies are discussed to overcome the problems and recent experimental results are presented as well as simulation results.