• Korea Multimedia Society
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• v.4 no.2
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• pp.5-14
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• 2000

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2001.11a
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• pp.143-153
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• 2001

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2003.10a
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• pp.29-46
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• 2003

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2003.10a
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• pp.329-342
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• 2003

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2002.10a
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• pp.255-263
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• 2002

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2002.10a
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• pp.3-18
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• 2002

• Journal of Korean Electronics
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• v.18 no.6
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• pp.14-19
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• 1998

• The KIPS Transactions:PartB
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• v.18B no.5
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• pp.249-254
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• 2011

FGS (fine granularity scalability) supporting scalability in MPEG-4 Part 2 is a scalable video coding scheme that provides bit-rate adaptation to varying network bandwidth thereby achieving of its optimal video quality. In this paper, we proposed FGS coding scheme which performs one more bit-plane coding for residue signal occured in the enhancement-layer of the basic FGS coding scheme. The experiment evaluated in terms of video quality scalability of the proposed FGS coding scheme by comparing with FGS coding scheme of the MPEG-4 verification model (VM-FGS). The comparison was conducted by analysis of PSNR values of three tested video sequences. The results showed that when using rate control algorithm VM5+, the proposed FGS coding scheme obtained Y, U, V PSNR of 0.4 dB, 9.4 dB, 9 dB averagely higher and when using fixed QP value 17, obtained Y, U, V PSNR of 4.61 dB, 20.21 dB, 16.56 dB averagely higher than the existing VM-FGS. From results, we found that the proposed FGS coding scheme has higher video quality scalability to be able to achieve video quality from minimum to maximum than VM-FGS.

• ETRI Journal
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• v.27 no.5
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• pp.533-538
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• 2005

We developed a pipelined scheduling technique of functional hardware and software modules for platform-based system-on-a-chip (SoC) designs. It is based on a modified list scheduling algorithm. We used the pipelined scheduling technique for a performance analysis of an MPEG4 video encoder application. Then, we applied it for architecture exploration to achieve a better performance. In our experiments, the modified SoC platform with 6 pipelines for the 32-bit dual layer architecture shows a 118% improvement in performance compared to the given basic SoC platform with 4 pipelines for the 16-bit single-layer architecture.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1999.11b
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• pp.261-266
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• 1999

본 논문에서는 인터넷 폰이나 디지털 이동통신에서와 같이 낮은 비트율이 요구되는 응용분야에서 사용될 수 있는 HVXC 부호화 및 복호화 알고리즘을 TMS320C6701 160MHz DSP를 사용하여 실시간 동작을 구현한 내용을 기술한다. 사용한 최적화 방법으로는 기본적으로 연산 시간이 많이 소요되는 함수 루틴에 대한 C 언어레벨의 최적화 및 어셈블리어 레벨의 최적화를 수행하였고, TMS320C6701 DSP 내부 프로그램 메모리를 프로그램 캐쉬로 사용하였다. 또한, 계산량이 많은 부분과 테이블 참조가 필요한 연산을DSP의 내부 데이터 메모리 영역에서 수행하여 소요시간을 단축하였으며, 음성신호 및 비트스트림의 입출력에는 background DMA(direct memory access) 방식을 이용하였다. 이와 같은 최적화결과 2kbps 및 4kbps의 비트율에서 압축 및 복원을 실시간으로 수행할 수 있다.