• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.297-305
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• 2007

In the paper, a Motion JPEG2000 coder which has been set as the standard for image compression by the Digital Cinema Initiatives (DCI), an organization composed of major movie studios was implemented into a target FPGA. The DWT (Discrete Wavelet Transform) based on lifting and the Tier 1 of EBCOT (Embedded Block Coding with Optimized Truncation) which are major functional modules of the JPEG2000 were setup with dedicated hardware. The Tier 2 process was implemented in software. For digital cinema the tile-size was set to support $1024\times1024$ pixels. To ensure the real-time operations, three entropy encoders were used. When Verilog-HDL was used for hardware, resources of 32,470 LEs in Altera's Stratix EP1S80 were used, and the hardware worked stably at the frequency of 150Mhz.

• Journal of Broadcast Engineering
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• v.14 no.1
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• pp.93-98
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• 2009

While the Motion JPEG2000 has been considered as a unique encoder for digital cinema due to its high quality coding and large screen format, the realization of a digital cinema system and its service cost enormous fund and time. In this paper a digital cinema transmission system with PC and RTP protocol over the Internet is proposed, and showed how tiles of moving images are transmitted, decoded independently and combined to reconstruct and display at a large screen for digital cinema service. The simulation has been carried out for tiles of 128${\times}$128, 256${\times}$256, 512${\times}$512, and 1024${\times}$1024 pixels. In the experiment, two clients of PC’s received and decoded tiles of video and constructed whole size of moving images successfully. The PSNR’s of the video ranges 30dB to 40dB at compression rate of 160:1 and 30dB to 50dB at and below 16:1, respectively. The result showed a possibility for the reconstruction of video in multi-vision.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.201-201
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• 2004

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.41-52
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• 2009

In Motion JPEG2000 encoding, huge bandwidth requirement of data memory access is the bottleneck in required system performance. For the alleviation of this bandwidth requirement, a new embedded compression(EC) algorithm with a little bit of image quality drop is devised. For both random accessibility and low latency, very simple and efficient entropy coding algorithm is proposed. We achieved significant memory bandwidth reductions (about 53${\sim}$81%) and reduced code-block memory to about half size through proposed multi-mode algorithms, without requiring any modification in JPEG2000 standard algorithm.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.43 no.8
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• pp.748-756
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• 2015

In this paper, we developed a miniaturized real time video compression system satisfying the military environment using ADV212 and FPGA. We present an efficient hardware design scheme for the weight reduction of the device and also a software solution to deal with noisy image signals. Experimental results show that the frame delay is reduced by a factor of 2 or 3 and the device's weight is decreased by a factor of 6 to 7. In order to prove the reliability for the military usage of this development, we examine the environmental test (MIL-STD-810G) and EMI test (MIL-STD-461F). Experimental results show that the developed system satisfies the requirements.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5C
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• pp.344-354
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• 2005

In this paper, we proposed a new lifting architecture for JPEG2000 and implemented to ASIC. We proposed a new cell to execute unit calculation of lifting using the property of lifting which is the repetitious arithmetic with same structure, and then recomposed the whole lifting by expanding it. After the operational sequence of lifting arithmetic was analyzed in detail and the causality was imposed for implementation to hardware, the unit cell was optimized. A new lifting kernel was organized by expanding simply the unit cell, and a lifting processor was implemented for Motion JPEG2000 using it. The implemented lifting kernel can accommodate the tile size of $1024{\times}1024$, and support both lossy compression using the (9,7) filter and lossless compression using (5,3) filter. Also, it has the same output rate as input rate, and can continuously output the wavelet coefficients of 4 types(LL, LH, HL, HH) at the same time. The implemented lifting processor completed a course of ASIC using $0.35{\mu}m$ CMOS library of SAMSUNG. It occupied about 90,000 gates, and stably operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the improved operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the performance can be identified in comparison with the previous researches and commercial IPs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.7C
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• pp.647-657
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• 2005

In this paper, we proposed a new lifting architecture for JPEG2000 and implemented to ASIC. We proposed a new cell to execute unit calculation of lifting using the property of lifting which is the repetitious arithmetic with same structure, and then recomposed the whole lifting by expanding it. After the operational sequence of lifting arithmetic was analyzed in detail and the causality was imposed for implementation to hardware, the unit cell was optimized. A new lifting kernel was organized by expanding simply the unit cell, and a lifting processor was implemented for Motion JPEG2000 using it. The implemented lifting kernel can accommodate the tile size of 1024$\times$1024, and support both lossy compression using the (9,7) filter and lossless compression using (5,3) filter. Also, it has the same output rate as input rate, and can continuously output the wavelet coefficients of 4 types(LL, LH, HL, HH) at the same time. The implemented lifting processor completed a course of ASIC using 0.35$\mu$m CMOS library of SAMSUNG. It occupied about 90,000 gates, and stably operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the improved operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the performance can be identified in comparison with the previous researches and commercial IPs.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.1
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• pp.1-9
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into a H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel for the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks. The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit or a field synchronized with the A/D converter. The implemented H/W used the 54％(12943) LAB(Logic Array Block) and 9％(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation. that is. processing 60 fields/sec(30 frames/sec).

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1803-1806
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• 2002

This paper describes an effective technique for lossless inter-frame video coding sequences based on a JPEG2000 CODEC. This technique has diminished the compression rate for lossless video coding. In this proposed method, firstly a predicted image for an in- put image is generated by motion estimation(ME), and then a difference image between the input image and the predicted image is calculated, and finally the difference image becomes an input image to a JPEG2000 encoder for lossless coding. Simulation results show the effectiveness of this method.

• ETRI Journal
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• v.37 no.3
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• pp.595-605
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• 2015

This paper proposes a robust, imperceptible block-based digital video watermarking algorithm that makes use of the Speeded Up Robust Feature (SURF) technique. The SURF technique is used to extract the most important features of a video. A discrete multiwavelet transform (DMWT) domain in conjunction with a discrete cosine transform is used for embedding a watermark into feature blocks. The watermark used is a binary image. The proposed algorithm is further improved for robustness by an error-correction code to protect the watermark against bit errors. The same watermark is embedded temporally for every set of frames of an input video to improve the decoded watermark correlation. Extensive experimental results demonstrate that the proposed DMWT domain video watermarking using SURF features is robust against common image processing attacks, motion JPEG2000 compression, frame averaging, and frame swapping attacks. The quality of a watermarked video under the proposed algorithm is high, demonstrating the imperceptibility of an embedded watermark.