The Transactions of the Korean Institute of Electrical Engineers D (대한전기학회논문지:시스템및제어부문D)

The Korean Institute of Electrical Engineers (대한전기학회)
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Hardware Architecture and its Design of Real-Time Video Compression Processor for Motion JPEG2000

Motion JPEG2000을 위한 실시간 비디오 압축 프로세서의 하드웨어 구조 및 설계

  • 서영호 (광운대학교 전자재료공학과) ;
  • 김동욱 (광운대학교 전자재료공학과)
  • Published : 2004.01.01
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Abstract

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into a H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel for the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks. The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit or a field synchronized with the A/D converter. The implemented H/W used the 54％(12943) LAB(Logic Array Block) and 9％(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation. that is. processing 60 fields/sec(30 frames/sec).

Keywords

References

  1. G. Knowles, 'VLSI Architectures for the Discrete Wavelet Transform', IEEE Electronic Letters, Vol. 26, No. 15, pp. 1184-1185, July 1990 https://doi.org/10.1049/el:19900766
  2. A.S. Lewis and G. Knowles, 'VLSI Architecture for 2-D Daubechies Wavelet Transform without Multipliers', IEEE Electronic Letters, Vol. 27, No. 2, pp. 171-173, Jan. 1991 https://doi.org/10.1049/el:19910110
  3. J. Fridman and E. S. Manolakos, 'Distributed Memory and Control VLSI Architectures for I-D Discrete Wavelet Transform', IEEE Workshop on Signal Processing Systems, pp. 388-397, 1994 https://doi.org/10.1109/VLSISP.1994.574763
  4. T.K. Truong, K.C. Hung, Y.J. Haung, and Y.H. Tseng, 'A New Architecture for the 2-D Discrete Wavelet Transform', IEEE Int'l Conf. of Communications Computers and Signal Processing, pp. 481-484, 1997 https://doi.org/10.1109/PACRIM.1997.620002
  5. C. Yu and S.J. Chen, 'Design of an Efficient VLSI Architecture for 2-D Discrete Wavelet Transform', IEEE Trans. on Consumer Electronics, Vol. 45, No. 1, pp. 135-140, Feb. 1999 https://doi.org/10.1109/30.754428
  6. M.H. Sheu, M.D. Shieh and S.W. Liu, 'A VLSI Architecture Design with Lower Hardware Cost and Less Memory for Separable 2-D Discrete Wavelet Transform', IEEE ISCAS'98, Vol. 5, pp, 457-460, 1998 https://doi.org/10.1109/ISCAS.1998.694531
  7. M. Vishiwanath, R. Michael and M.J. Irwin, 'VLSI Architecture for the Discrete Wavelet Transform', IEEE Trans. on Circuits and Systems-It: Analog and Digital Signal Processing, Vol. 42, No.5, pp. 305-316, May 1995 https://doi.org/10.1109/82.386170
  8. J. Chen and M.A. Bayoumi, 'A Scalable Systolic Array Architecture for 2-D Discrete Wavelet Transforms', IEEE Proc. of Midwest Symp. on Circuits and Systems, Vol. 2, pp, 303-312, 1996 https://doi.org/10.1109/MWSCAS.1995.510290
  9. W. Ravasi, M. Mattavelli, D.J. Mlynek, A. Butter, and A Soudagar, 'Wavelet Image Compression for Mobile/Portable Applications', IEEE Trans. on Consumer Electronics, Vol. 45, No.3, pp. 794-803, Aug. 1999 https://doi.org/10.1109/30.793608
  10. S. Masud and J.V. McCanny, 'Wavelet Packet Transform for System-on-Chip Application', IEEE Proc. on ICASSP, Vol. 6, pp. 3287-3290, 2000 https://doi.org/10.1109/ICASSP.2000.860102
  11. A.M. Reza and R.D.Turney, 'FPGA Implementation of 2D Wavelet Transform', IEEE Can! of Signals, Systems and Computers, pp. 584-588, 1999 https://doi.org/10.1109/ACSSC.1999.832397
  12. W. Jiang and A.Ortega, 'Lifting factorization-based discrete wavelet transform architecture design,' IEEE Trans. Circuits Syst, Video Technol., vol. 11, pp. 651-657, May 2001 https://doi.org/10.1109/76.920194
  13. C. Diou, L. Torres, and M. Robert, 'A wavelet core for video processing,' presented at the IEEE Int. Conf. Image Process., Sept. 2000 https://doi.org/10.1109/ICIP.2000.899406
  14. G. Lafruit, L. Nachtergaele, J. Bormans, M. Engels, and I. Bolsens, 'Optimal memory organization for scalable texture codecs in MPEG-4, IEEE Trans. Circuits Syst, Video Technol., vol. 9, pp. 218-243, Mar. 1999 https://doi.org/10.1109/76.752091
  15. K. Andra, C. Chakrebarti, and T.Acharya, A VLSI architecture for lifting-based forward and inverse wavelet transform,' IEEE Trans., on Signal Processing, vol. 50, no. 4, Apr 2002 https://doi.org/10.1109/78.992147
  16. M. Ravasi, L. Tenze, and M. Mattavelli, 'A scalable and programmable architecture for 2-D DWT decoding,' IEEE Trans. Circuits Syst. Video Technol., vol. 12, no. 8, Aug. 2002 https://doi.org/10.1109/TCSVT.2002.800863
  17. A. Said and W.A. Pearlman, 'A New, Fast and Efficient Image codec Based on Set Partitioning in Hierarchical Trees', IEEE Trans. on Circuits and Systems for Video Technology, Vol. 6. No.3, pp. 243-250, June 1996 https://doi.org/10.1109/76.499834
  18. S.F. Hsiao, Y.C. Tai, and K.H. Chang, 'VLSI Design of an Efficient Embedded Zerotree Wavelet Coder with Function of Digital Watermarking', IEEE Trans. on Consumer Electronics, Vol. 46, No.3, pp. 628-636, August 2000 https://doi.org/10.1109/30.883423
  19. B. Parhami, 'Computer Arithmetic : Algorithm and Hardware Desig', Oxford University Press, 2000
  20. IEEE Trans. on Consumer Electronics v.46 no.3 VLSI Design of an Efficient Emvedded Zerotree Wavelet Coder with Function of Digital Watermarking S.F.Hsiao;Y.C.Tai;K.H.Chang https://doi.org/10.1109/30.883423
  21. Computer Arithmetic : Algorithm and Hardware Designs B.Parhami