• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.58-65
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and variable point 2D SAD hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the SAD unit and its parallel operations using pattern information, the proposed IME instructions support not only full search algorithms but also other fast search algorithms. The hardware size is 25.5K gates for each Processing Element Group (PEG) which has 128 SAD Processor Elements (PEs). The proposed ASIP has been verified by the Synopsys Processor Designer and implemented by the Design Compiler using the IBM 90nm process technology. The hardware size is 453K gates for the IME unit and the operating frequency is 188MHz for 1080p@30 frame in real time. The proposed ASIP can reduce the hardware size about 26% and the number of operation cycles about 18%.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.2
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• pp.138-148
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• 2001

Digital Video (DV) coding standards for digital video cassette recorder are based mainly on DCT and variable length coding. DV has low hardware complexity but high compressed bit rate of about 26 Mb/s. Thus, it is necessary to encode video with low complex video coding at the studios and then transcode compressed video into MPEG-2 for video-on-demand system. Because these coding methods exploit DCT, transcoding in the DCT domain can reduce computational complexity by excluding duplicated procedures. In transcoding DV into MPEC-2 intra coding, multiplying matrix by transformed data is used for 4:1:1-to-4:2:2 chroma format conversion and the conversion from 2-4-8 to 8-8 DCT mode, and therefore enables parallel processing. Variance of sub block for MPEG-2 rate control is computed completely in the DCT domain. These are verified through experiments. We estimate motion hierarchically using DCT coefficients for transcoding into MPEG-2 inter coding. First, we estimate motion of a macro block (MB) only with 4 DC values of 4 sub blocks and then estimate motion with 16-point MB using IDCT of 2$\times$2 low frequencies in each sub block, and finish estimation at a sub pixel as the fifth step. ME with overlapped search range shows better PSNR performance than ME without overlapping.

• Journal of the Earthquake Engineering Society of Korea
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• v.18 no.3
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• pp.151-160
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• 2014

Probabilistic tsunami hazard analysis (PTHA) is based on the approach of probabilistic seismic hazard analysis (PSHA) which is performed using various seismotectonic models and ground-motion prediction equations. The major difference between PTHA and PSHA is that PTHA requires the wave parameters of tsunami. The wave parameters can be estimated from tsunami propagation analysis. Therefore, a tsunami simulation analysis was conducted for the purpose of evaluating the wave parameters required for the PTHA of Uljin nuclear power plant (NPP) site. The tsunamigenic fault sources in the western part of Japan were chosen for the analysis. The wave heights for 80 rupture scenarios were numerically simulated. The synthetic tsunami waveforms were obtained around the Uljin NPP site. The results show that the wave heights are closely related with the location of the fault sources and the associated potential earthquake magnitudes. These wave parameters can be used as input data for the future PTHA study of the Uljin NPP site.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.6
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• pp.1-8
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• 2000

This paper describes an algorithm for semantic video object tracking using semi automatic method. In the semi automatic method, a user specifies an object of interest at the first frame and then the specified object is to be tracked in the remaining frames. The proposed algorithm consists of three steps: object boundary projection, uncertain area extraction, and boundary refinement. The object boundary is projected from the previous frame to the current frame using the motion estimation. And uncertain areas are extracted via two modules: Me error-test and color similarity test. Then, from extracted uncertain areas, the exact object boundary is obtained by boundary refinement. The simulation results show that the proposed video object extraction method provides efficient tracking results for various video sequences compared to the previous methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.6
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• pp.6-15
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• 2009

In this paper, a new 4-way search window is designed for the high-performance 2D PE architecture in H.264 Motion Estimation(ME) to improve the memory bandwidth. While existing 2D PE architectures reuse the overlapped data of adjacent search windows scanned in 1 or 3-way, the new window utilizes the overlapped data of adjacent search windows as well as adjacent multiple scanning (window) paths to enhance the reusage of retrieved search window data. In order to scan adjacent windows and multiple paths instead of single raster and zigzag scanning of adjacent windows, bidirectional row and column window scanning results in the 4-way(up. down, left, right) search window. The proposed 4-way search window could improve the reuse of overlapped window data to reduce the redundancy access factor by 3.1, though the 1/3-way search window redundantly requires $7.7{\sim}11$ times of data retrieval. Thus, the new 4-way search window scheme enhances the memory bandwidth by $70{\sim}58%$ compared with 1/3-way search window. The 2D PE architecture in H.264 ME for 4-way search window consists of $16{\times}16$ pe array. computing the absolute difference between current and reference frames, and $5{\times}16$ reusage array, storing the overlapped data of adjacent search windows and multiple scanning paths. The reference data could be loaded upward and downward into the new 2D PE depending on scanning direction, and the reusage array is combined with the pe array rotating left as well as right to utilize the overlapped data of adjacent multiple scan paths. In experiments, the new implementation of 4-way search window on Magnachip 0.18um could deal with the HD($1280{\times}720$) video of 1 reference frame, $48{\times}48$ search area and $16{\times}16$ macroblock by 30fps at 149.25MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2091-2098
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• 2010

This paper proposes a hologram data compression scheme that uses the existing image/video compression techniques, in which the existing techniques are modified appropriately to fit to the characteristics of hologram. In this paper we use CGH as the hologram data. The proposed scheme uses the generation characteristics of a CGH to consist of a pre-processing, spatial segmentation of a CGH, frequency-transformation with 2D-DCT (2-dimensional discrete cosine transform), and motion estimation and residual image generation in the frequency-domain. It uses H.264/AVC, the lossless compressor BinHex, and a linear quantizer that we have made. From the experiments the proposed scheme showed the image quality of about 25.4 dB at the compression ratio of 10:1 and about 16.5dB at 90:1 compression ratio.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.6
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• pp.575-584
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• 2002

This paper presents a novel DCT-based embedded zero-tree coding and optimal bit allocation algorithm for image sequence coding. In order to fully utilize the structure of the conventional standard coding algorithm and improve the coding efficiency, motion estimation and compensation(ME/MC)-DCT hybrid coding structure and a modified zero-tree coding algorithm are applied. After the rearrangement DCT coefficients into pyramidal structure according to their significance on the decoded image quality, the modified embedded zero-tree coding is performed on layered coefficients. Moreover, for a given overall bit rates, a new optimal bit control scheme is proposed to achieve the best decoded image quality in the consecutive frames. The rate control scheme can also provide the equal quality of decoded image with the control of bit rate and distortion for each frame. The various simulation results are provided to evaluate the coding performance of the proposed scheme.