• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.5
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• pp.267-273
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• 2012

The short-range communication module was developed in this paper which is suitable for the point-to-multipoint circumstances of 40 terminals communicating frequently in about 50 meters. The media access control layer of this communication module using asynchronous time-division multiplexing provides a fast and robust performance even in the worst case of simultaneous transmission events, and low packet error rate was measured a in LOS (Line-of-sight) circumstance by adding the function of acknowledge response to media access control layer. The difference test was carried out in order to measure the performance of point-to-multipoint communication. Two communication modules are respectively measured and graphed in 10 branches to 40 branches. The communication module developed in this paper showed a faster performance than the commercial Zigbee module in the specific case presented in this paper. Especially, in over 20 branches showed wide differences of the transmission speed. This results is caused by more network overhead of Zigbee whose wider applications needs the network layer and applicaiton layer besides media access control layer. Also, the asynchronous time-division multiplexing proposed in this paper are more suitable than CSMA-CA of Zigbee module when a lot of module ought to be frequently communicated in small area.

• Journal of the Korea Society of Computer and Information
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• v.16 no.2
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• pp.141-151
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• 2011

This paper suggests the Facility Management System for plant factory promising to be a core technology of the agriculture in the future. This system makes diagnoses that status from sensors or facilities in the factory for exact operation and monitors the internal environment with the control status in real-time. It is expected that we could operate a plant factory safely and effectively by using the system. The system consists of the data management module, the context provider module, the context interpreter module, the service provider module, the data storage and user interface. The system provide with the failure diagnosis service, the facility control service, and the high-reliability monitoring service via the interactions between above modules. The failure diagnosis service determines whether the sensors or facility devices are in failure or not, and informs the administrator of their conditions. The facility control service is activated in case if the facilities need to be managed during the diagnosis for failure or malfunction processes. The high-reliability monitoring service provides the administrator with verified data through the failure diagnosis service. Then we confirmed that the suggested system operates correctly through the system simulation.

• Journal of the Korea Society of Computer and Information
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• v.24 no.12
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• pp.25-33
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• 2019

This paper presents a novel evolutionary framework for optimizing a bio-inspired fully dynamic neurocontroller for the maneuverable flapping flight of a simulated bird-sized ornithopter robot which takes advantage of the morphological computation and mechansensory feedback to improve flight stability. In order to cope with the difficulty of generating robust flapping flight and its maneuver, the wing of robot is modelled as a series of sub-plates joined by passive torsional springs, which implements the simplified version of feathers attached to the forearm skeleton. The neural controller is designed to have a bilaterally symmetric structure which consists of two fully connected neural network modules receiving mirrored sensory inputs from a series of flight navigation sensors as well as feather mechanosensors to let them participate in pattern generation. The synergy of wing compliance and its sensory reflexes gives a possibility that the robot can feel and exploit aerodynamic forces on its wings to potentially contribute to the agility and stability during flight. The evolved robot exhibited target-following flight maneuver using asymmetric wing movements as well as its tail, showing robustness to external aerodynamic disturbances.

• Archives of Plastic Surgery
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• v.39 no.5
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• pp.540-545
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• 2012

Background Patients have anxiety and fear of complications due to general anesthesia. Through new instruments and local anesthetic drugs, a variety of anesthetic methods have been introduced. These methods keep hospital costs down and save time for patients. In particular, the target-controlled infusion (TCI) system maintains a relatively accurate level of plasma concentration, so the depth of anesthesia can be adjusted more easily. We conducted this study to examine whether intravenous anesthesia using the TCI system with propofol and remifentanil would be an effective method of anesthesia in breast augmentation. Methods This study recruited 100 patients who underwent breast augmentation surgery from February to August 2011. Intravenous anesthesia was performed with 10 mg/mL propofol and 50 ${\mu}g/mL$ remifentanil simultaneously administered using two separate modules of a continuous computer-assisted TCI system. The average target concentration was set at 2 ${\mu}g/mL$ and 2 ng/mL for propofol and remifentanil, respectively, and titrated against clinical effect and vital signs. Oxygen saturation, electrocardiography, and respiratory status were continuously measured during surgery. Blood pressure was measured at 5-minute intervals. Information collected includes total duration of surgery, dose of drugs administered during surgery, memory about surgery, and side effects. Results Intraoperatively, there was transient hypotension in two cases and hypoxia in three cases. However, there were no serious complications due to anesthesia such as respiratory difficulty, deep vein thrombosis, or malignant hypertension, for which an endotracheal intubation or reversal agent would have been needed. All the patients were discharged on the day of surgery and able to ambulate normally. Conclusions Our results indicate that anesthetic methods, where the TCI of propofol and remifentanil is used, might replace general anesthesia with endotracheal intubation in breast augmentation surgery.

• Korean Journal of Remote Sensing
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• v.36 no.5_2
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• pp.881-891
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• 2020

Recently, the Ministry of Land, Infrastructure and Transport and the Ministry of Science and ICT are developing the Land Observation Satellite (CAS-500) to meet increased demand for high-resolution satellite images. Expected image products of CAS-500 includes precision orthoimage, Digital Surface Model (DSM), change detection map, etc. The quality of these products is determined based on the geometric accuracy of satellite images. Therefore, it is important to make precision geometric corrections of CAS-500 images to produce high-quality products. Geometric correction requires the Ground Control Point (GCP), which is usually extracted manually using orthoimages and digital map. This requires a lot of time to acquire GCPs. Therefore, it is necessary to automatically extract GCPs and reduce the time required for GCP extraction and orthoimage generation. To this end, the Precision Image Processing (PIP) System was developed for CAS-500 images to minimize user intervention in GCP extraction. This paper explains the products, processing steps and the function modules and Database of the PIP System. The performance of the System in terms of processing speed, is also presented. It is expected that through the developed System, precise orthoimages can be generated from all CAS-500 images over the Korean peninsula promptly. As future studies, we need to extend the System to handle automated orthoimage generation for overseas regions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.687-698
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• 2001

This paper presents a three dimensional stacked pad area away (PAA) package configuration as an implementation method of radio frequency (RF) circuits. 224MHz RF circuits of intelligence traffic system(ITS) were constructed with the stacked PAA RF pakage configuration. In the process of manufacturing the stacked PAA RF pakage, RF circuits were partitioned to subareas following their function and operating frequency. Each area of circuits separated to each subunits. The operating characteristics of RF PAA package module and the electrical properties of each subunits were examined. The measurement of electrical parameters for solder balls which were interconnects for stacked PAA RF packages showed that the parasitic capacitance and inductance were 30fF and 120pH, respectively, which might be negligible in PAA RF packaging system. HP 4396B network/spectrum analyzer revealed that the amplification gain of a receiver and transmitter at 224 MHz was 22dB and 27dB, respectively. The gain was 3dB lower than designed values. The difference was probably generated from fabrication process of the circuits by employing commercial standard

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.1
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• pp.116-126
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• 2011

In this paper, we present a multi-media processor which can decode multiple-format video standards. The designed processor is evaluated with optimized MPEG-2, MPEG-4, and AVS (Audio video standard). There are two approaches for developing of real-time video decoders. First, hardware-based system is much superior to a processor-based one in execution time. However, it takes long time to implement and modify hardware systems. On the contrary, the software-based video codecs can be easily implemented and flexible, however, their performance is not so good for real-time applications. In this paper, in order to exploit benefits related to two approaches, we designed a processor called ASIP(Application specific instruction-set processor) for video decoding. In our work, we extracted eight common modules from various video decoders, and added several multimedia instructions to the processor. The developed processor for video decoders is evaluated with the Synopsys platform simulator and a FPGA board. In our experiment, we can achieve about 37% time saving in total decoding time.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.24-35
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• 2012

In this paper, we propose a dynamic lane control scheme with a traffic predictor module and a rate controller for reconciling with commercial optical PHY modules in energy efficient optical Ethernet systems. The commercial high speed optical Ethernet system capable of 40/100Gbps employs 4 or 10 multiple optical transceivers over WDM or multiple optical links. Each of the transceivers is always turned on even if the link is idle. To save energy, we propose the dynamic lane control scheme. It allows that several links may be entirely turned off in a low traffic load and frames are handled on the remaining active links. To preserve the byte order even if the number of active links may be changed, we propose a rate controller to be sat on the reconciliation sublayer. The main role of the controller is to insert null byte streams into the xGMII of inactive lanes. For the PHY module, the null input streams corresponding to inactive lanes will be disregarded on inactive PMDs. It is very handy to implement the rate controller module with MAC in FPGA without any modification of commercial PHYs. It is very crucial to determine the number of active links based on the fluctuated traffic load, we provide a simple traffic predictor based on both the current transmission buffer size and the past one with different weighting factors for adapting to the traffic load fluctuation. Using the OMNET++ simulation framework, we provide several performance results in terms of the energy consumption.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.43-54
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• 2007

This paper presents design and verification of a face detection hardware for real time application. Face detection algorithm detects rough face position based on already acquired feature parameter data. The hardware is composed of five main modules: Integral Image Calculator, Feature Coordinate Calculator, Feature Difference Calculator, Cascade Calculator, and Window Detection. It also includes on-chip Integral Image memory and Feature Parameter memory. The face detection hardware was verified by using S3C2440A CPU of Samsung Electronics, Virtex4LX100 FPGA of Xilinx, and a CCD Camera module. Our design uses 3,251 LUTs of Xilinx FPGA and takes about 1.96${\sim}$0.13 sec for face detection depending on sliding-window step size, when synthesized for Virtex4LX100 FPGA. When synthesized on Magnachip 0.25um ASIC library, it uses about 410,000 gates (Combinational area about 345,000 gates, Noncombinational area about 65,000 gates) and takes less than 0.5 sec for face realtime detection. This size and performance shows that it is adequate to use for embedded system applications. It has been fabricated as a real chip as a part of XF1201 chip and proven to work.