• Korean Journal of Remote Sensing
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• v.36 no.5_2
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• pp.881-891
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• 2020

Recently, the Ministry of Land, Infrastructure and Transport and the Ministry of Science and ICT are developing the Land Observation Satellite (CAS-500) to meet increased demand for high-resolution satellite images. Expected image products of CAS-500 includes precision orthoimage, Digital Surface Model (DSM), change detection map, etc. The quality of these products is determined based on the geometric accuracy of satellite images. Therefore, it is important to make precision geometric corrections of CAS-500 images to produce high-quality products. Geometric correction requires the Ground Control Point (GCP), which is usually extracted manually using orthoimages and digital map. This requires a lot of time to acquire GCPs. Therefore, it is necessary to automatically extract GCPs and reduce the time required for GCP extraction and orthoimage generation. To this end, the Precision Image Processing (PIP) System was developed for CAS-500 images to minimize user intervention in GCP extraction. This paper explains the products, processing steps and the function modules and Database of the PIP System. The performance of the System in terms of processing speed, is also presented. It is expected that through the developed System, precise orthoimages can be generated from all CAS-500 images over the Korean peninsula promptly. As future studies, we need to extend the System to handle automated orthoimage generation for overseas regions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.687-698
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• 2001

This paper presents a three dimensional stacked pad area away (PAA) package configuration as an implementation method of radio frequency (RF) circuits. 224MHz RF circuits of intelligence traffic system(ITS) were constructed with the stacked PAA RF pakage configuration. In the process of manufacturing the stacked PAA RF pakage, RF circuits were partitioned to subareas following their function and operating frequency. Each area of circuits separated to each subunits. The operating characteristics of RF PAA package module and the electrical properties of each subunits were examined. The measurement of electrical parameters for solder balls which were interconnects for stacked PAA RF packages showed that the parasitic capacitance and inductance were 30fF and 120pH, respectively, which might be negligible in PAA RF packaging system. HP 4396B network/spectrum analyzer revealed that the amplification gain of a receiver and transmitter at 224 MHz was 22dB and 27dB, respectively. The gain was 3dB lower than designed values. The difference was probably generated from fabrication process of the circuits by employing commercial standard

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.1
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• pp.116-126
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• 2011

In this paper, we present a multi-media processor which can decode multiple-format video standards. The designed processor is evaluated with optimized MPEG-2, MPEG-4, and AVS (Audio video standard). There are two approaches for developing of real-time video decoders. First, hardware-based system is much superior to a processor-based one in execution time. However, it takes long time to implement and modify hardware systems. On the contrary, the software-based video codecs can be easily implemented and flexible, however, their performance is not so good for real-time applications. In this paper, in order to exploit benefits related to two approaches, we designed a processor called ASIP(Application specific instruction-set processor) for video decoding. In our work, we extracted eight common modules from various video decoders, and added several multimedia instructions to the processor. The developed processor for video decoders is evaluated with the Synopsys platform simulator and a FPGA board. In our experiment, we can achieve about 37% time saving in total decoding time.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.24-35
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• 2012

In this paper, we propose a dynamic lane control scheme with a traffic predictor module and a rate controller for reconciling with commercial optical PHY modules in energy efficient optical Ethernet systems. The commercial high speed optical Ethernet system capable of 40/100Gbps employs 4 or 10 multiple optical transceivers over WDM or multiple optical links. Each of the transceivers is always turned on even if the link is idle. To save energy, we propose the dynamic lane control scheme. It allows that several links may be entirely turned off in a low traffic load and frames are handled on the remaining active links. To preserve the byte order even if the number of active links may be changed, we propose a rate controller to be sat on the reconciliation sublayer. The main role of the controller is to insert null byte streams into the xGMII of inactive lanes. For the PHY module, the null input streams corresponding to inactive lanes will be disregarded on inactive PMDs. It is very handy to implement the rate controller module with MAC in FPGA without any modification of commercial PHYs. It is very crucial to determine the number of active links based on the fluctuated traffic load, we provide a simple traffic predictor based on both the current transmission buffer size and the past one with different weighting factors for adapting to the traffic load fluctuation. Using the OMNET++ simulation framework, we provide several performance results in terms of the energy consumption.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.43-54
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• 2007

This paper presents design and verification of a face detection hardware for real time application. Face detection algorithm detects rough face position based on already acquired feature parameter data. The hardware is composed of five main modules: Integral Image Calculator, Feature Coordinate Calculator, Feature Difference Calculator, Cascade Calculator, and Window Detection. It also includes on-chip Integral Image memory and Feature Parameter memory. The face detection hardware was verified by using S3C2440A CPU of Samsung Electronics, Virtex4LX100 FPGA of Xilinx, and a CCD Camera module. Our design uses 3,251 LUTs of Xilinx FPGA and takes about 1.96${\sim}$0.13 sec for face detection depending on sliding-window step size, when synthesized for Virtex4LX100 FPGA. When synthesized on Magnachip 0.25um ASIC library, it uses about 410,000 gates (Combinational area about 345,000 gates, Noncombinational area about 65,000 gates) and takes less than 0.5 sec for face realtime detection. This size and performance shows that it is adequate to use for embedded system applications. It has been fabricated as a real chip as a part of XF1201 chip and proven to work.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.2
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• pp.65-73
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• 2008

The characterization process for the accurate color reproduction in mobile phone with camera and LCD is popular. The camera and LCD characterization, gamut mapping process is necessary to map the camera's input color stimulus, CIEXYZ value, into the LCD's output color stimulus. Each characterization is the process estimating the relation between input and output signals. In case of LCD, because of output device, the output color stimulus for the arbitrary input signal can be measured by spectro-radiometer However, in the camera, as the input device, the characterization is an inaccurate and needs the manual works in the process obtaining the output signal because the input signal can not be generated. Moreover, after gamut mapping process, the noise is increased because the optimized gamma tone curve of camera for the noise is distorted by the characterization. Thus, this paper proposed the system of obtaining the output signal of camera and the method of gamma correction for the noise. The camera's output signal is obtained by RGB values of patches from captured the color chart image. However, besides the illumination, the error for the location of the chart in the viewfinder is generated when many camera modules are captured the chart. The method of correcting the position to correct the error from manual works. The position of camera is estimated by captured image. This process and moving of camera is accomplished repeatedly, and the optimized position can be obtained. Moreover, the lightness curve of camera output is corrected partly to reduce the noise from the characterization process.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.107-115
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• 2013

Smart appliances with multi-media and telecommunication equipments provide users complicated convenience functions. On the contrary, 8-bit controller-based low performance electronics still cannot afford such multimedia and telecommunication. If we find a way to have low-end electronics connected and provide complicated functions, they can be also made "smart". Fortunately, 8-bit controllers used in low-end appliances have UART, which can be connected to any of BlueTooth, Wi-Fi and ZigBee communication modules which can, in turn, communicate with smart devices. Any communication module can be attached to the low-end electronics due to the variety of smart devices' connectivity at the other side. Although the convenience functions seem complicated, they are actually macros in a script form composed of micro commands which implement the base functions of appliances. Since the kinds of the base functions are not that many, the low-end electronic appliances will become "smart" if their control program can be extended to execute sequentially the micro commands in any combination. Such simple innovation has not seen the world, until now due to the overhead of the additionally required hardware such as display devices and buttons. The high-quality display and touch screen functionalities of smart devices can replace the required hardware, and remove the overhead completely. In fact, the low-end appliances become smart as if an "evolution kit" is newly equipped.

• Journal of IKEEE
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• v.22 no.3
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• pp.858-861
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• 2018

In this paper, we propose the development of a small $360^{\circ}$ oral scanner lens module. The proposed small $360^{\circ}$ oral scanner lens module consists of a small $360^{\circ}$ high resolution(4MegaPixel) lens optical system, a 15mm image sensor unit, and a small $360^{\circ}$ mouth scanner lens external shape. A small $360^{\circ}$ high resolution lens optical system produces a total of nine lenses, the outer diameter of the lens not less than 15mm for use by children through the ages of adulthood. Light drawn by a small $360^{\circ}$ high resolution lens optical system is $90^{\circ}$ flexion so that image images are delivered to image sensors. The 15mm image sensor unit sends the converted value to the ISP(Image Signal Processor) of the embedded board after an image array through the column and the row address of the image sensor. The small $360^{\circ}$ mouth scanner lens outer shape was designed to fix the race to the developed lens. Results from authorized testing agencies to assess the performance of proposed small $360^{\circ}$ oral scanner lens modules, The optical resolving power of $360^{\circ}$ lens was more than 30% at 150 cycles/mm, $360^{\circ}$ lens angle was $360^{\circ}$ in vertical direction, $42^{\circ}{\sim}85^{\circ}$ in vertical direction, and lens distortion rate was 5% or less. It produced the same result as the world's highest level.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.4
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• pp.362-369
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• 2018

In this paper, we propose a procedure to multiple SNS channels automatic streaming through multiple output channels including the output channel of an external streaming server. The multiple SNS channels automatic streaming server includes an output management module for controlling the transmission of video contents to RELAY module that establish two or more output channels. In this paper, we experimented by separate with HD and FHD video using RELAY module in multiple SNS channel automatic streaming. In stream modules using RELAY module of HD video, when the publisher client and the player client and the RELAY module are 1 channel, the occupancy rate of CPU is 0.6% and the occupancy rate of heap memory is 0.3%(20 Mbyte). When the publisher client and the player client and the RELAY module are 183 channels, the occupancy rate of CPU is 99.9% and the occupancy rate of heap memory is 45.8%(3.7Gbyte). Therefore, the paper is not limited to the size of the streaming server by extending the output channel from which the video is transmitted to the output channel of the external streaming server. And a process of allocating an output channel of an external streaming server to an output channel through which an video is transmitted can be easily performed, so that an efficient output channel management can be performed even when a plurality of videos are transmitted.