• Proceedings of the Korean Society of Near Infrared Spectroscopy Conference
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• 2001.06a
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• pp.1619-1619
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• 2001

Ourwork aims to assess the content of dry matter, protein, cell wall parameters and water soluble carbohydrates in forages without having to handle samples, transport them to a laboratory, dry, grind and chemically analyze them. for this purpose, the concept of fresh forage analysis under field conditions by means of compact integrated NIRS InGaAs-diode array instruments on small plot harvesters is being evaluated for plant breeding trials. This work was performed with the world first commercial experimental forage plot harvester equipped with a NIRS module for the collection, compression, and scanning of forage samples (including automatic referencing and dark current measure ments). It was used for harvesting and analyzing a number of typical forage grass and forage legume plot trials. After NIRS measurements in the field each sample was again analyzed in the laboratory by means of a conventional grating spectrometer equipped with Si-and PbS-detectors. Conventional laboratory analysis of the samples was restricted to dry matter (DM) content by means of oven drying at 105. Routine chemometric procedures were then employed to assess the comparative accuracy and precision of the DM assessments in the spectral range between 950 and 1650nm by the NIRS diode array as well as by the conventional NIRS scanning instrument. The results of this study confirmed that the type of NIRS diode array instrument employed here functioned well even in rugged field operations. further refinements proved to be necessary for optimizing the automatic filling of the sample compartment to adjust for the wide variation in forage material under conditions of extremely low or high harvest yields. The error achieved in calibrating the apparatus for forages of typical DM content proved to be satisfactory (SECV < 1.0). Possibly as a consequence of higher sampling errors, its performance in atypical forages with elevated DM contents was less satisfactory. The error level obtained on the conventional grating NIR spectrometer was similar to that of the diode array instrument for both types of forage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3C
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• pp.102-111
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• 2005

In this paper, we propose an advanced hardware architecture for the fast inter prediction engine of the video coding standard MPEG-4 AVC. We describe the algorithm and derive the hardware architecture emphasizing and real time operation of the quarter_pel based motion estimation. The fast inter prediction engine is composed of block segmentation, motion estimation, motion compensation, and the fast quarter_pel calculator. The proposed architecture has been verified by ARM-interfaced emulation board using Excalibur & Virtex2 FPGA, and also by synthesis on Samsung 0.18 um CMOS technology. The synthesis result shows that the proposed hardware can operate at 62.5MHz. In this case, it can process about 88 QCIF video frames per second. The hardware is being used as a core module when implementing a complete MPEG-4 AVC video encoder chip for real-time multimedia application.

• Journal of Microbiology and Biotechnology
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• v.19 no.3
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• pp.257-264
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• 2009

A $\beta$-agarase gene, agaB34, was functionally cloned from the genomic DNA of a marine bacterium, Agarivorans albus YKW-34. The open reading frame of agaB34 consisted of 1,362 bp encoding 453 amino acids. The deduced amino acid sequence, consisting of a typical N-terminal signal peptide followed by a catalytic domain of glycoside hydrolase family 16 (GH-16) and a carbohydrate-binding module (CBM), showed 37-86% identity to those of agarases belonging to family GH-16. The recombinant enzyme (rAgaB34) with a molecular mass of 49 kDa was produced extracellularly using Escherichia coli $DH5{\alpha}$ as a host. The purified rAgaB34 was a $\beta$-agarase yielding neoagarotetraose (NA4) as the main product. It acted on neoagarohexaose to produce NA4 and neoagarobiose, but it could not further degrade NA4. The maximal activity of rAgaB34 was observed at $30^{\circ}C$ and pH 7.0. It was stable over pH 5.0-9.0 and at temperatures up to $50^{\circ}C$. Its specific activity and $k_{cat}/K_m$ value for agarose were 242 U/mg and $1.7{\times}10^6/sM$, respectively. The activity of rAgaB34 was not affected by metal ions commonly existing in seawater. It was resistant to chelating reagents (EDTA, EGTA), reducing reagents (DTT, $\beta$-mercaptoethanol), and denaturing reagents (SDS and urea). The E. coli cell harboring the pUC18-derived agarase expression vector was able to efficiently excrete agarase into the culture medium. Hence, this expression system might be used to express secretory proteins.

• Journal of Advanced Navigation Technology
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• v.16 no.4
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• pp.619-626
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• 2012

One-way Network-RTK(Real Time Kinematics) is considered as a method which can satisfy moving vehicle's recently-required high accuracy and mobility. When we use one-way Network RTK for vehicle navigation, multiple cells-based system is required to provide the service continuously in wide area. The rover which moves through various cells inevitably experiences a correction discontinuity, which is not eliminated by the DD(Double Difference) method and to cause 13cm(horizontal) and 48cm(vertical) position error. We suggest three solutions to reduce this discontinuity, which are identification of master RS with neighbor networks, duplication of communication module to receive corrections from other cells, and ambiguity adjustment between neighbor cells. All of our suggestions reduce the error to 1/4 wavelength in measurement and 3cm in position-domain, and we suggest the ambiguity adjustment is the best when we consider the extendibility of service area and the cost of rover device.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.585-593
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• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.3
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• pp.681-686
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• 2017

Degradation is commonly observed in field-aged PV modules due to corrosion of the photovoltaic ribbon. The reduced performance is caused by a loss of fill factor due to the high series resistance in the PV ribbon. This study aimed to mitigate the degradation by corrosion using five sacrificial anodes - Al, Zn and their alloys - to identify the most effective material to mitigate the corrosion of the PV ribbon. The corrosion behavior of the five sacrificial anode materials were examined by open circuit potential measurements, potentiodynamic polarization tests, and galvanic current density and potential measurements using a zero resistance ammeter. Immersion tests for 120 hours were also conducted using materials and damp heat test tests were performed for 1500 hours using 4 cell mini modules. The Al-3Mg and Al-3Zn-1Mg sacrificial anodes had a low corrosion rate and reduced drop in power, making then suitable for long-term use.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.109-114
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• 2013

Power MOSFET (metal-oxide semiconductor field-effect transistor) are widely used in power electronics applications, such as BLDC (Brushless Direct Current) motor and power module, etc. For the conventional power MOSFET device structure, there exists a tradeoff relationship between specific on-state resistance and breakdown voltage. In order to overcome the tradeoff relationship, a non-uniform super-junction (SJ) trench MOSFET (TMOSFET) structure for an optimal design is proposed in this paper. It is required that the specific on-resistance of non-uniform SJ TMOSFET is less than that of uniform SJ TMOSFET under the same breakdown voltage. The idea with a linearly graded doping profile is proposed to achieve a much better electric field distribution in the drift region. The structure modelling of a unit cell, the characteristic analyses for doping density, and potential distribution are simulated by using of the SILVACO TCAD 2D device simulator, Atlas. As a result, the non-uniform SJ TMOSFET shows the better performance than the uniform SJ TMOSFET in the specific on-resistance at the class of 100V.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.59-65
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• 2008

This paper proposed a H.264 deblocking filter for the portable low-power multimedia. In H.264 deblocking filter, total 8 input pixels in filtering operations needs own filtering operation process respectively, and each filtering process has common structures for each filtering operation. By sharing common filter coefficients and registers, we have designed and implemented an smaller gated module, and moreover filtering operations are skipped on some or whole pixels what if we use some specific condition to operate filtering modules that need lots of operations. In the core of filtering modules, we achieve 33.31% and 10.85% gate count reduction compared with those of filtering modules of the conventional deblocking filter papers. The proposed low-power deblocking filter is implemented by using samsung 0.35um standard cell library technology, the maximum operationh frequency is 108MHz, and the maximum throughput is 33.03 frames/s with CCIR601 image format.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.136-139
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• 2011

The conventional semiconductor equipment has adopted SRAM module as the test pattern memory, which has a simple design and does not require refreshing. However, SRAM has its disadvantages as it takes up more space as its capacity becomes larger, making it difficult to meet the requirements of large memories and compact size. if DRAM is adopted as the semiconductor inspection equipment, it takes up less space and costs less than SRAM. However, DRAM is also disadvantageous because it requires the memory cell refresh, which is not suitable for the semiconductor examination equipments that require correct timing. Therefore, In this paper, we will proposed an algorithm for punctuality guarantee of memory-free inspection equipment using DDR2 SDRAM. And we will produced memory controller using punctuality guarantee algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.3
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• pp.55-61
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• 2000

This paper presents an efficient hardware architecture of frame memory interface in MPEG-2 video encoder. To reduce the size of memory buffers between SDRAM and the frame memory module, the number of clocks needed for each memory access is minimized with dual bank operation and burst length change. By allocating the remaining cycles not used by SDRAM access, to the random access cycle, the internal buffer size, the data bus width, and the size of the control logic can be minimized. The proposed architecture is operated with 54MHz clock and designed with the VT $I^{тм}$ 0.5 ${\mu}{\textrm}{m}$ CMOS TLM standard cell library. It is verified by comparing the test vectors generated by the c-code model with the simulation results of the synthesized circuit. The buffer area of the proposed architecture is reduced to 40 % of the existing architecture.