• Title/Summary/Keyword: Modular multiplier

Search Result 88, Processing Time 0.026 seconds

Implementation of a LSB-First Digit-Serial Multiplier for Finite Fields GF(2m) (유한 필드 GF(2m)상에서의 LSB 우선 디지트 시리얼 곱셈기 구현)

  • Kim, Chang-Hun;Hong, Chun-Pyo;U, Jong-Jeong
    • The KIPS Transactions:PartA
    • /
    • v.9A no.3
    • /
    • pp.281-286
    • /
    • 2002
  • In this paper we, implement LSB-first digit-serial systolic multiplier for computing modular multiplication $A({\times})B$mod G ({\times})in finite fields GF $(2^m)$. If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of regularity, modularity, and unidirectional data flow, it shows good extension characteristics with respect to m and L.

A Study on the Design of Highly Parallel Multiplier using VCGM (VCGM를 사용한 고속병렬 승산기 설계에 관한 연구)

  • 변기영;성현경;김흥수
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.27 no.6A
    • /
    • pp.555-561
    • /
    • 2002
  • In this paper, a new designed circuit of highly parallel multiplier using standard basis over $GF(2^m)$ is presented. Prior to construct the multiplier circuit, we provide the Vector Code Generate Module(VCGM) that generate each vector codes for multiplication. Using these VCGMs, we can get all vector codes necessary for operation and modular sum up each independent corresponding basis, respectively. Following the equations in this paper, we can design generalized multiplier to m. For the proposed circuit in this parer, we show the example in $GF(2^4)$ using VCGMs. In this paper, we build a multiplier with VCGMs, AND blocks, and EX-OR blocks. Therefore the proposed circuit is easy to generalize for m and advantageous for VLSI. Also, it need no memory element and the latency not less fewer then other circuit. We verify the proposed circuit by functional simulation and show its result. Finally, we compare the circuit composition with other works and show its result with a table.

Design of MSB-First Digit-Serial Multiplier for Finite Fields GF(2″) (유한 필드 $GF(2^m)$상에서의 MSB 우선 디지트 시리얼 곱셈기 설계)

  • 김창훈;한상덕;홍춘표
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.27 no.6C
    • /
    • pp.625-631
    • /
    • 2002
  • This paper presents a MSB-first digit-serial systolic array for computing modular multiplication of A(x)B(x) mod G(x) in finite fields $GF(2^m)$. From the MSB-first multiplication algorithm in $GF(2^m)$, we obtain a new data dependence graph and design an efficient digit-serial systolic multiplier. For circuit synthesis, we obtain VHDL code for multiplier, If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has much more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of unidirectional data flow and regularity, it shows good extension characteristics with respect to m and L.

Modular Design of Analog Hopfield Network (아날로그 홉필드 신경망의 모듈형 설계)

  • Dong, Sung-Soo;Park, Seong-Beom;Lee, Chong-Ho
    • Proceedings of the KIEE Conference
    • /
    • 1991.11a
    • /
    • pp.189-192
    • /
    • 1991
  • This paper presents a modular structure design of analog Hopfield neural network. Each multiplier consists of four MOS transistors which are connected to an op-amp at the front end of a neuron. A pair of MOS transistor is used in order to maintain linear operation of the synapse and can produce positive or negative synaptic weight. This architecture can be expandable to any size neural network by forming tree structure. By altering the connections, other nework paradigms can also be implemented using this basic modules. The stength of this approach is the expandability and the general applicability. The layout design of a four-neuron fully connected feedback neural network is presented and is simulated using SPICE. The network shows correct retrival of distorted patterns.

  • PDF

Design of LSB Multiplier using Cellular Automata (셀룰러 오토마타를 이용한 LSB 곱셈기 설계)

  • 하경주;구교민
    • Journal of Korea Society of Industrial Information Systems
    • /
    • v.7 no.3
    • /
    • pp.1-8
    • /
    • 2002
  • Modular Multiplication in Galois Field GF(2/sup m/) is a basic operation for many applications, particularly for public key cryptography. This paper presents a new architecture that can process modular multiplication on GF(2/sup m/) per m clock cycles using a cellular automata. Proposed architecture is more efficient in terms of the space and time than that of systolic array. Furthermore it can be efficiently used for the hardware design for exponentiation computation.

  • PDF

New Multiplier using Montgomery Algorithm over Finite Fields (유한필드상에서 몽고메리 알고리즘을 이용한 곱셈기 설계)

  • 하경주;이창순
    • Proceedings of the Korea Society for Industrial Systems Conference
    • /
    • 2002.06a
    • /
    • pp.190-194
    • /
    • 2002
  • Multiplication in Galois Field GF(2/sup m/) is a primary operation for many applications, particularly for public key cryptography such as Diffie-Hellman key exchange, ElGamal. The current paper presents a new architecture that can process Montgomery multiplication over GF(2/sup m/) in m clock cycles based on cellular automata. It is possible to implement the modular exponentiation, division, inversion /sup 1)/architecture, etc. efficiently based on the Montgomery multiplication proposed in this paper. Since cellular automata architecture is simple, regular, modular and cascadable, it can be utilized efficiently for the implementation of VLSI.

  • PDF

FPGA Implementation of RSA Public-Key Cryptographic Coprocessor for Restricted System

  • Kim, Mooseop;Park, Yongje;Kim, Howon
    • Proceedings of the IEEK Conference
    • /
    • 2002.07c
    • /
    • pp.1551-1554
    • /
    • 2002
  • In this paper, the hardware implementation of the RSA public-key cryptographic algorithm is presented. The RSA cryptographic algorithm is depends on the computation of repeated modular exponentials. The Montgomery algorithm is used and modified to reduce hardware resources and to achieve reasonable operating speed for smart card. An efficient architecture for modular multiplications based on the array multiplier is proposed. We have implemented a 10240it RSA cryptographic processor based on proposed scheme in IESA system developed for smart card emulating system. As a result, it is shown that proposed architecture contributes to small area and reasonable speed for smart cards.

  • PDF

Circuit Design of Modular Multiplier for Fast Exponentiation (고속 멱승을 위한 모듈라 곱셈기 회로 설계)

  • 하재철;오중효;유기영;문상재
    • Proceedings of the Korea Institutes of Information Security and Cryptology Conference
    • /
    • 1997.11a
    • /
    • pp.221-231
    • /
    • 1997
  • 본 논문에서는 고속 멱승을 위한 모듈라 곱셈기를 시스토릭 어레이로 설계한다. Montgomery 알고리듬 및 시스토릭 어레이 구조를 분석하고 공통 피승수 곱셈 개념을 사용한 변형된 Montgomery 알고리듬에 대해 시스토릭 어레이 곱셈기를 설계한다. 제안 곱셈기는 각 처리기 내부 연산을 병렬화 할 수 있고 연산 자체도 간단화 할 수 있어 시스토릭 어레이 하드웨어 구현에 유리하며 기존의 곱셈기를 사용하는 것보다 멱승 전체의 계산을 약 0.4배내지 0.6배로 감소시킬 수 있다.

  • PDF

Modular Multiplier based on Cellular Automata over $GF({2^m})$ (셀룰라 오토마타를 이용한 $GF({2^m})$상의 곱셈기$^1$)

  • 이형목;김현성;전준철;하경주;구교민;김남연;유기영
    • Proceedings of the Korean Information Science Society Conference
    • /
    • 2001.10a
    • /
    • pp.709-711
    • /
    • 2001
  • 본 논문에서는 유한 확대 체 GF($^{m}$ )상에서 셀룰라 오토마타를 이용한 곱셈기 구조를 제안한다. 제안된 구조는 기약 다항식으로 AOP(All One Polynomial)의 특성을 사용하고 LSB방식으로 곱셈 연산을 수행한다. 제안된 곱셈기는 지연시간으로 m+1을 갖는 임계경로로는 1- $D_{AND}$+1- $D_{XOR}$를 갖는다. 특히 구조가 정규성, 모듈성, 병렬성을 가지기 때문에 VLSI구현에 효율적이다.적이다.

  • PDF

Low System Complexity Parallel Multiplier for a Class of Finite Fields based on AOP (시스템 복잡도 개선을 위한 AOP 기반의 병렬 유한체 승산기)

  • 변기영;나기수;윤병희;최영희;한성일;김흥수
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.29 no.3A
    • /
    • pp.331-336
    • /
    • 2004
  • This study focuses on the hardware implementation of fast and low-system-complexity multiplier over GF(2$^{m}$ ). From the properties of an irreducible AOP of degree m. the modular reduction in GF(2$^{m}$ ) multiplicative operation can be simplified using cyclic shift operation. And then, GF(2$^{m}$ ) multiplicative operation can be established using the away structure of AND and XOR gates. The proposed multiplier is composed of m(m+1) 2-input AND gates and (m+1)$^2$ 2-input XOR gates. And the minimum critical path delay is Τ$_{A+}$〔lo $g_2$$^{m}$ 〕Τ$_{x}$ proposed multiplier obtained have low circuit complexity and delay time, and the interconnections of the circuit are regular, well-suited for VLSI realization.n.