• Journal of Power Electronics
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• 제17권1호
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• pp.242-252
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• 2017

This paper deals with the blocking of DC-fault current during DC cable short-circuit conditions in HVDC (High-Voltage DC) transmission systems utilizing Modular Multilevel Converters (MMCs), where a new SubModule (SM) topology circuit for the MMC is proposed. In this SM circuit, an additional Insulated-Gate Bipolar Translator (IGBT) is required to be connected at the output terminal of a conventional SM with a half-bridge structure, hereafter referred to as HBSM, where the anti-parallel diodes of additional IGBTs are used to block current from the grid to the DC-link side. Compared with the existing MMCs based on full-bridge (FB) SMs, the hybrid topologies of HBSM and FBSM, and the clamp-double SMs, the proposed topology offers a lower cost and lower power loss while the fault current blocking capability in the DC short-circuit conditions is still provided. The effectiveness of the proposed topology has been validated by simulation results obtained from a 300-kV 300-MW HVDC transmission system and experimental results from a down-scaled HVDC system in the laboratory.

• 대한수학회보
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• 제31권2호
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• pp.237-242
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• 1994

One of the most well-known geometric lattices is a partition lattice. Every upper interval of a partition lattice is a partition lattice. The whitney numbers of a partition lattices are the Stirling numbers, and the characteristic polynomial is a falling factorial. The set of partitions with a single non-trivial block containing a fixed element is a Boolean sublattice of modular elements, so the partition lattice is supersolvable in the sense of Stanley [6]. In this paper, we rephrase four results due to Heller[1] and Murty [4] in terms of matroids and give several characterizations of partition lattices. Our notation and terminology follow those in [8,9]. To clarify our terminology, let G, be a finte geometric lattice. If S is the set of points (or rank-one flats) in G, the lattice structure of G induces the structure of a (combinatorial) geometry, also denoted by G, on S. The size vertical bar G vertical bar of the geometry G is the number of points in G. Let T be subset of S. The deletion of T from G is the geometry on the point set S/T obtained by restricting G to the subset S/T. The contraction G/T of G by T is the geometry induced by the geometric lattice [cl(T), over ^1] on the set S' of all flats in G covering cl(T). (Here, cl(T) is the closure of T, and over ^ 1 is the maximum of the lattice G.) Thus, by definition, the contraction of a geometry is always a geometry. A geometry which can be obtained from G by deletions and contractions is called a minor of G.

• Journal of Electrical Engineering and information Science
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• 제2권6호
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• pp.48-55
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• 1997

Advances in VLSI technology have brought us completely new design principles for the high-performance switching fabrics including ATM switches. From a practical point of view, port scalability of ATM switches emerges as an important issue while complexity and performance of the switches have been major issues in the switch design. In this paper, we propose a cost-effective approach to modular ATM switch design which provides the good scalability. Taking advantages of both time-division and space-division switch architectures, we propose a practically implementable large scale ATM switch architecture. We present a scalable shared buffer type switch for a building block and its expansion method. In our design, a large scale ATM switch is realized by interconnecting the proposed shared buffer switches in three stages. We also present an efficient control mechanism of the shared buffers, synchronization method for the switches in each stage, and a flow control between stages. It is believed that the proposed approach will have a significant impact on both improving the ATM switch performance and enhancing the scalability of the switch with a new cost-effective scheme for handling the traffic congestion. We show that the proposed ATM switch provides an excellent performance and that its cell delay characteristic is comparable to output queueing which provides the best performance in cell delay among known approaches.

• 한국시뮬레이션학회논문지
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• 제11권2호
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• pp.1-16
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• 2002

The need for network security is being increasing due to the development of information communication and internet technology. In this paper, firewall models, operating system models and other network component models are constructed. Each model is defined by basic or compound model, referencing DEVS formalism. These models and the simulation environment are implemented with MODSIM III, a general purpose, modular, block-structured high-level programming language which provides direct support for object-oriented programming and discrete-event simulation. In this simulation environment with representative attacks, the following three attacks are generated, SYN flooding and Smurf attack as an attack type of denial of service, Mail bomb attack as an attack type of e-mail. The simulation is performed with the models that exploited various security policies against these attacks. The results of this study show that the modeling method of packet filtering system, proxy system, unix and windows NT operating system. In addition, the results of the simulation show that the analysis of security performance according to various security policies, and the analysis of correlation between availability and confidentiality according to security empowerment.

• Nuclear Engineering and Technology
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• 제45권4호
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• pp.439-458
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• 2013

REX-10 is a fully-passive small modular reactor in which the coolant flow is driven by natural circulation, the RCS is pressurized by a steam-gas pressurizer, and the decay heat is removed by the PRHRS. To confirm design decisions and analyze the transient responses of an integral PWR such as REX-10, a thermal-hydraulic system code named TAPINS (Thermal-hydraulic Analysis Program for INtegral reactor System) is developed in this study. Based on a one-dimensional four-equation drift-flux model, TAPINS incorporates mathematical models for the core, the helical-coil steam generator, and the steam-gas pressurizer. The system of difference equations derived from the semi-implicit finite-difference scheme is numerically solved by the Newton Block Gauss Seidel (NBGS) method. TAPINS is characterized by applicability to transients with non-equilibrium effects, better prediction of the transient behavior of a pressurizer containing non-condensable gas, and code assessment by using the experimental data from the autonomous integral effect tests in the RTF (REX-10 Test Facility). Details on the hydrodynamic models as well as a part of validation results that reveal the features of TAPINS are presented in this paper.

• 융합정보논문지
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• 제9권1호
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• pp.68-73
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• 2019

본 연구는 스마트분전반 MG(;Micro-Grid) 구성의 중심축으로 모듈형 하이브리드 발전원과 DC버스를 통하여 링크를 갖으며 표준소켓을 사용하여 불법연결을 감지 차단하는 기능을 부여하고, 전력계통의 안정화를 달성함을 목적으로 한다. 전력변환장치, 스마트분전반, 통합제어시스템의 개발과 효율적인 수요관리가 필요하며, MG 전체시스템과의 호환성이 절실하다. 이는 공통 전력 연결 규약으로 안전하고 누구나 연결을 쉽게 할 수 있는 하이브리드발전시스템으로 데이터 관리가 용이해지고 다양한 제조사의 시스템 확대설치에 대한 대비가 가능하다.

• 공학교육연구
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• 제26권1호
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• pp.37-44
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• 2023

Recently, the Internet of Things is attracting attention as an important key technology of the 4th Industrial Revolution, and SW education using physical computing is suggested as a good alternative to supplement the problems raised by beginners in programming education. Among the many teaching tools that can be used for physical computing education, MODI is a modular manufacturing tool that anyone can easily assemble like Lego. MODI is a teaching tool that can improve learners' achievement by linking a self-linked block-type code editor called MODI Studio to lay the foundation for programming in a relatively small amount of time and immediately check the results in person. In this paper, a physical computing education method using MODI was designed to be applied to basic programming courses for programming beginners and applied to after-school classes for middle school students. As a result, it was found that students' interest and satisfaction were much higher in physical computing classes using MODI than in text-based programming classes. It can be seen that physical computing education that allows beginners to see and feel the results in person is more effective than grammar-oriented text programming, and it can have a positive effect on improving basic programming skills by increasing students' participation.

• 한국컴퓨터정보학회논문지
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• 제25권10호
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• pp.261-268
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• 2020

본 논문에서는 장애 유형별 청소년 소프트웨어 교육을 위한 효과적인 소프트웨어 교육 모델을 제안한다. 이 소프트웨어 교육 모델은 4단계 과정으로 구성된다. 첫 번째 단계에서는 특수교육 교육과정에서 소프트웨어 교육 영역을 비교 분석한 결과를 기반으로 장애 유형별 청소년 소프트웨어 교육을 위한 교육과정을 도출한다. 두 번째 단계에서는 지적장애와 중복장애가 없는 시각, 청각, 지체 장애로 구분하여 장애 청소년의 효과적인 소프트웨어 교육을 위한 성취기준을 도출한다. 세 번째 단계에서는 도출한 성취기준에 따라 장애 유형별 장애 특성을 반영하여 코딩 로봇 알버트 기반의 언플러그드 컴퓨팅, 피지컬 컴퓨팅, 블록/텍스트 코딩으로 구성된 모듈식 교재를 개발한다. 네 번째 단계에서는 이 교재를 학교 현장에 적용하여 장애 청소년들이 일상생활에서 접하는 다양한 문제를 스스로 절차적이고 논리적으로 사고할 수 있도록 체험 중심의 소프트웨어 교육을 실시한다. 그리고 장애 청소년의 성취도 평가와 설문조사를 통한 결과를 분석하여 지적장애 82.3%, 시각장애 78.8%, 청각장애 90.9%, 지체장애 78.8%의 장애 청소년들이 '중' 수준 이상의 성취도를 달성하였음을 보인다. 이러한 결과는 본 논문에서 제안한 장애 청소년을 위한 소프트웨어 교육 모델이 장애 청소년의 컴퓨팅 사고력 향상에 매우 효과적임을 검증한 것이다.

• 한국정보통신학회논문지
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• 제9권8호
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• pp.1741-1748
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• 2005

본 논문에서는 암호 기능과 함께 데이터 인증 기능을 지원하는 OCB(offsetest codebook)-AES(advanced encryption) 암호 알고리즘을 VLSI로 설계하고 성능을 분석하였다. OCB-AES 암호 알고리즘은 기존 암호 시스템에서 암호 알고리즘과 인증에 구별된 알고리즘과 하드웨어를 사용함에 따른 많은 연산 시간과 하드웨어 문제를 해결하였다. 면적 효율적인 모듈화된 오프셋 생성기와 태그 생성 회로를 내장한 OCB-AES 프로세서는 IDEC 삼성 0.35um CMOS 공정으로 설계되었으며 약 55,700 게이트로 구성되며, 80MHz의 동작주파수로 930 Mbps의 암${\cdot}$복호율을 갖는다. 그리고 무결성과 인증에 사용되는 128 비트 태그를 생성하는데 소요되는 클록사이클 수는 (m+2)${\times}$(Nr+1)이다. 여기서 m은 메시지의 블록 수이며, Nr은 AES 암호 알고리즘의 라운드 수이다. 설계된 프로세서는 높은 암${\times}$복효율과 면적 효율성으로 IEEE 802.11i 무선 랜과 모바일용 SoC(System on chip)에 암호 처리를 위한 소프트 IP(Intellectual Property)로 적용 가능하다.

• 한국정보통신학회논문지
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• 제25권3호
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• pp.419-426
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• 2021

NIST FIPS 186-2에 정의된 GF(p) 상의 5 가지 체 크기 (192, 224, 256, 384, 521 비트)와 8 가지의 산술연산 동작모드 (ECPSM, ECPA, ECPD, MA, MS, MM, MI, MD)를 지원하는 고성능 타원곡선 암호 프로세서 HP-ECCP를 설계하였다. HP-ECCP가 부채널 공격에 내성을 갖도록 만들기 위해, 타원곡선 점 스칼라 곱셈에 사용되는 개인키의 해밍웨이트에 무관하게 점 덧셈과 점 두배 연산이 균일하게 수행되는 수정된 left-to-right 이진 알고리듬을 적용하여 설계했다. 또한, 타원곡선 점 연산에 핵심이 되는 모듈러 곱셈 연산의 고성능 하드웨어 구현을 위해 Karatsuba-Ofman 곱셈 알고리듬, Lazy 축약 알고리듬, Nikhilam 나눗셈 알고리듬을 적용하여 설계했다. HP-ECCP를 180 nm CMOS 표준 셀 라이브러리로 합성한 결과 67 MHz의 동작 주파수에서 620,846 등가 게이트로 구현되었으며, 체 크기 256 비트의 ECPSM이 초당 2,200회 계산될 수 있는 것으로 평가되었다.