• Title/Summary/Keyword: Mode Complexity

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A Frequency Domain DV-to-MPEG-2 Transcoding (DV에서 MPEG-2로의 주파수 영역 변환 부호화)

  • Kim, Do-Nyeon;Yun, Beom-Sik;Choe, Yun-Sik
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.38 no.2
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    • pp.138-148
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    • 2001
  • Digital Video (DV) coding standards for digital video cassette recorder are based mainly on DCT and variable length coding. DV has low hardware complexity but high compressed bit rate of about 26 Mb/s. Thus, it is necessary to encode video with low complex video coding at the studios and then transcode compressed video into MPEG-2 for video-on-demand system. Because these coding methods exploit DCT, transcoding in the DCT domain can reduce computational complexity by excluding duplicated procedures. In transcoding DV into MPEC-2 intra coding, multiplying matrix by transformed data is used for 4:1:1-to-4:2:2 chroma format conversion and the conversion from 2-4-8 to 8-8 DCT mode, and therefore enables parallel processing. Variance of sub block for MPEG-2 rate control is computed completely in the DCT domain. These are verified through experiments. We estimate motion hierarchically using DCT coefficients for transcoding into MPEG-2 inter coding. First, we estimate motion of a macro block (MB) only with 4 DC values of 4 sub blocks and then estimate motion with 16-point MB using IDCT of 2$\times$2 low frequencies in each sub block, and finish estimation at a sub pixel as the fifth step. ME with overlapped search range shows better PSNR performance than ME without overlapping.

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A Study on Automatic Interface Generation by Protocol Mapping (Protocol Mapping을 이용한 인터페이스 자동생성 기법 연구)

  • Lee Ser-Hoon;Kang Kyung-Goo;Hwang Sun-Young
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.8A
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    • pp.820-829
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    • 2006
  • IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Due to the request for high performance of current mobile systems, embedded SoC design needs a multi-processor to manage problems of high complexity and the data processing such as multimedia, DMB and image processing in real time. Interface module for communication between system buses and processors are required, since many IPs employ different protocols. High performance processors require interface module to minimize the latency of data transmission during read-write operation and to enhance the performance of a top level system. This paper proposes an automatic interface generation system based on FSM generated from the common protocol description sequence of a bus and an IP. The proposed interface does not use a buffer which stores data temporally causing the data transmission latency. Experimental results show that the area of the interface circuits generated by the proposed system is reduced by 48.5% on the average, when comparing to buffer-based interface circuits. Data transmission latency is reduced by 59.1% for single data transfer and by 13.3% for burst mode data transfer. By using the proposed system, it becomes possible to generate a high performance interface circuit automatically.

Adaptive Irregular Binning and Its Application to Video Coding Scheme Using Iterative Decoding (적응 불규칙 양자화와 반복 복호를 이용한 비디오 코딩 방식에의 응용)

  • Choi Kang-Sun
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.4C
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    • pp.391-399
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    • 2006
  • We propose a novel low complexity video encoder, at the expense of a complex decoder, where video frames are intra-coded periodically and frames in between successive intra-coded frames are coded efficiently using a proposed irregular binning technique. We investigate a method of forming an irregular binning which is capable of quantizing any value effectively with only small number of bins, by exploiting the correlation between successive frames. This correlation is additionally exploited at the decoder, where the quality of reconstructed frames is enhanced gradually by applying POCS(projection on the convex sets). After an image frame is reconstructed with the irregular binning information at the proposed decoder, we can further improve the resulting quality by modifying the reconstructed image with motion-compensated image components from the neighboring frames which are considered to contain image details. In the proposed decoder, several iterations of these modification and re-projection steps can be invoked. Experimental results show that the performance of the proposed coding scheme is comparable to that of H.264/AVC coding in m mode. Since the proposed video coding does not require motion estimation at the encoder, it can be considered as an alternative for some versions of H.264/AVC in applications requiring a simple encoder.

Flexible Body Dynamics Analysis of Agricultural Tractor Using 4-Post Road Simulator (4-Post Road Simulator 를 이용한 농용 트랙터의 유연 다물체 동역학 해석)

  • Park, Ji Soo;Lee, Kang Wook;Cho, Chong Youn;Yoon, Ji Won;Shin, Jai Yoon
    • Transactions of the KSME C: Technology and Education
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    • v.3 no.2
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    • pp.83-88
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    • 2015
  • Agricultural tractors are utilized on rough road such as rice paddy field. Therefore, static and dynamic load should be considered when simulating structural analysis with finite element analysis (FEA). But it consumes a lot of time and effort to measure dynamic load because of difficulty and complexity in modeling various field working load conditions and kinematics of machinery. In this paper, to reduce the efforts, 4-post road simulator is developed for agricultural tractor like modeling commercial vehicle. In proving ground test in our facility, I measured acceleration of front/rare axle and strain of body frame to validate input loads. The acceleration is used for defining input loads. And strain is validated with dynamics analysis including mode superposition method. As a result, I was able to calculate 4-post input road profiles, which represent similar proving ground profile with good reliability.

Multi-layered Gap Measurement on In-Vessel Cerium Retention Using Ultrasonic Wave Reflective Pattern Analysis and Frequency Diversity Signal Processing (초음파 반사 패턴과 주파수 대역 분할 신호처리를 이용한 다층구조인 노내 간극 측정)

  • Koo, Kil-Mo;Sim, Cheul-Mu;Kim, Jong-Hwan;Kim, Sang-Baik;Kim, Hee-Dong;Park, Chi-Seung
    • Journal of the Korean Society for Nondestructive Testing
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    • v.20 no.4
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    • pp.314-321
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    • 2000
  • A gap between a $Al_2O_3/Fe$ thermite and lower head vessel is formed in the lower-plenum arrested vessel attack(LAVA) experiment which is the 1st phase study of simulation of naturally arrested vessel attack in vessel(SONATA-IV). The gap measurement using a conventional ultrasonic method would be lack of a reliability due to the structure complexity and the metallurgical grain size change of the lower head HAZ occurred by a thermite $Al_2O_3/Fe$ melt or a $Al_2O_3$ melt at $2300^{\circ}C$. The grain echoes having false signals and lower S/N ratio signals are detected due to a multiple scattering, a mode conversion and an attenuation of a ultrasonic resulted from at the interface of increased grain size zone. In this test, the signals pattern was classified to understand the behavior of the ultrasonic in a multi-layer specimen of solid-liquid-solid of assuming that the thermite and the lower head vessel is immersed. The polarity threshold algorithm of frequency diversity gives us the enhancement about 6dB of the ratio S/N.

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Design of QDI Model Based Encoder/Decoder Circuits for Low Delay-Power Product Data Transfers in GALS Systems (GALS 시스템에서의 저비용 데이터 전송을 위한 QDI모델 기반 인코더/디코더 회로 설계)

  • Oh Myeong-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.1 s.343
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    • pp.27-36
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    • 2006
  • Conventional delay-insensitive (DI) data encodings usually require 2N+1 wires for transferring N-bit. To reduce complexity and power dissipation of wires in designing a large scaled chip, an encoder and a decoder circuits, where N-bit data transfer can be peformed with only N+l wires, are proposed. These circuits are based on a quasi delay-insensitive (QDI) model and designed by using current-mode multiple valued logic (CMMVL). The effectiveness of the proposed data transfer mechanism is validated by comparisons with conventional data transfer mechanisms using dual-rail and 1-of-4 encodings through simulation at the 0.25 um CMOS technology. In general, simulation results with wire lengths of 4 mm or larger show that the CMMVL scheme significantly reduces delay-power product ($D{\ast}P$) values of the dual-rail encoding with data rate of 5 MHz or more and the 1-of-4 encoding with data rate of 18 MHz or more. In addition, simulation results using the buffer-inserted dual-rail and 1-of-4 encodings for high performance with the wire length of 10 mm and 32-bit data demonstrate that the proposed CMMVL scheme reduces the D*P values of the dual-rail encoding with data rate of 4 MHz or more and 1-of-4 encoding with data rate of 25 MHz or more by up to $57.7\%\;and\;17.9\%,$ respectively.

Establishment of Fire Reliability Assessment Method for Structural Strength (화재시 구조강도에 대한 신뢰성 평가방법의 정립)

  • Park, Chang-Kyu
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.18 no.10
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    • pp.54-62
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    • 2017
  • This paper describes the behavior and failure probability of the basic structural members in a fire for the fire safety assessment of offshore structures. A fire safety assessment can be accomplished by comparing the fire resistance of the members with the fire severity of the heat load due to fire. The fire severity is represented as the maximum temperature of the members using the Eurocode 1 standard fire curve and heat transfer equation. On the other hand, the fire resistance is the limiting temperature calculated by a simplified formula in the case of simple structural members. Considering the complexity of FPSOs and offshore structures, a general-purpose structural analysis program should be used and the limiting temperature obtained by analyzing the structural strength of the members through an elasto-plastic analysis with a large deflection, and compared with the maximum temperature. Also, the equality of these two methods of evaluating the fire resistance was confirmed by comparing them. Following three criteria, the strength, serviceability and stability, three failure modes, namely the first failure of a hinge, large deflection and buckling, were chosen. The failure temperature was verified for each failure mode. using the AFOSM method in the equation of the fire severity and fire resistance, thereby giving the failure probability of the member. By applying these processes to the example of a beam and plate, the behavior of the structure and failure (temperature?) of each failure mode can be determined.

Measures for Improvement of RAM Target Value Setting Methods for Submarine Weapon Systems (잠수함 무기체계 RAM 목표 값 설정 방식의 개선방안)

  • Jung, Sun-uk;Shim, Hang-geun;Choi, Myoung-jin
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.21 no.4
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    • pp.419-427
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    • 2020
  • In the case of large combined weapon systems, such as submarines, the application, and verification of methods of setting the reliability, availability, and maintainability (RAM) target values for conventional weapon systems are limited. Submarines are complex weapon systems with the characteristics of the diversity of operation mode summary and mission profiles (OMS/MP) as well as equipment complexity because they are composed of multiple weapon systems, such as sonar systems and armed systems. Therefore, this study analyzed the development cases of existing weapon systems, i.e., the RAM target value-setting cases, and derived the problems and limitations of the cases to present measures to improve the setting and verification of the ram target values of submarines. In addition, submarines operate around the world and have different operating and maintenance conditions. Therefore, a submarine's ram target values should be set and verified centering on the mission essential equipment and mission critical equipment, instead of all components that constitute weapon systems. This study examined a method to verify the required performance RAM target-value setting, considering the characteristics of submarines as well as the physical performance requirements for the systems and equipment of submarines that must be considered when implementing national defense acquisition projects for submarines.

Blind Adaptive Equalization of Partial Response Channels (부분 응답 채널에서의 블라인드 적응 등화 기술에 관한 연구)

  • 이상경;이재천
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.26 no.11A
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    • pp.1827-1840
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    • 2001
  • In digital data transmission/storage systems, the compensation for channel distortion is conducted normally using a training sequence that is known a priori to both the sender and receiver. The use of the training sequences results in inefficient utilization of channel bandwidth. Sometimes, it is also impossible to send training sequences such as in the burst-mode communication. As such, a great deal of attention has been given to the approach requiring no training sequences, which has been called the blind equalization technique. On the other hand, to utilize the limited bandwidth effectively, the concept of partial response (PR) signaling has widely been adopted in both the high-speed transmission and high-density recording/playback systems such as digital microwave, digital subscriber loops, hard disk drives, digital VCRs and digital versatile recordable disks and so on. This paper is concerned with blind adaptive equalization of partial response channels whose transfer function zeros are located on the unit circle, thereby causing some problems in performance. Specifically we study how the problems of blind channel equalization associated with the PR channels can be improved. In doing so, we first discuss the existing methods and then propose new structures for blind PR channel equalization. Our structures have been extensively tested by computer simulation and found out to be encouraging in performance. The results seem very promising as well in terms of the implementation complexity compared to the previous approach reported in literature.

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A Defect Prevention Model based on SW-FMEA (SW-FMEA 기반의 결함 예방 모델)

  • Kim Hyo-Young;Han Hyuk-Soo
    • Journal of KIISE:Software and Applications
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    • v.33 no.7
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    • pp.605-614
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    • 2006
  • The success of a software development project can be determined by the use of QCD. And as a software's size and complexity increase, the importance of early quality assurance rises. Therefore, more effort should be given to prevention, as opposed to correction. In order to provide a framework for the prevention of defects, defect detection activities such as peer review and testing, along with analysis of previous defects, is required. This entails a systematization and use of quality data from previous development efforts. FMEA, which is utilized for system safety assurance, can be applied as a means of software defect prevention. SW-FMEA (Software Failure Mode Effect Analysis) attempts to prevent defects by predicting likely defects. Presently, it has been applied to requirement analysis and design. SW-FMEA utilizes measured data from development activities, and can be used for defect prevention on both the development and management sides, for example, in planning, analysis, design, peer reviews, testing, risk management, and so forth. This research discusses about related methodology and proposes defect prevention model based on SW-FMEA. Proposed model is extended SW-FMEA that focuses on system analysis and design. The model not only supports verification and validation effectively, but is useful for reducing defect detection.