• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.7 no.10
• /
• pp.2527-2543
• /
• 2013

A novel steganographic QR code algorithm, which not only coveys the secret into the widely-used QR barcode but also preserves the readability of QR content and the capability of error correction, is presented in this article. Different from the conventional applications for QR barcode, the designed algorithm conceals the secret into the QR modules directly by exploiting the error correction capability. General browsers can read the QR content from the QR code via barcode readers; however, only the authorized receiver can further reveal the secret from the QR code directly. The new mechanism can convey a larger secret payload along with adjustment of the QR version and error correction level. Moreover, the blind property allows the receiver to reveal the secret without the knowledge of the embedded position of modules. Experimental results demonstrate that the new algorithm is secure, efficient and feasible for the low-power QR readers and mobile devices.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.9B
• /
• pp.1082-1091
• /
• 2011

Power-reduction techniques based on DVFS(Dynamic Voltage and Frequency Scaling) are crucial for lengthening operating times of battery powered mobile systems. This paper proposes an optimal DVFS scheduling algorithm for decoders with memory size limitation on display buffer, which is realistic constraints not properly touched in the previous works. Furthermore, we mathematically prove that the proposed algorithm is optimal in the limited display buffer and limited clock frequency model, and also can be used for feasibility check. Simulation results show the proposed algorithm outperformed the previous heuristic algorithms by 7% in average, and the performance of all algorithms using display buffers saturates at about 10 frame size.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.18 no.5
• /
• pp.229-235
• /
• 2018

As of in the year of 2016, 40 million ARM processors are being shipped everyday and more than 86 billion ARM processors are mounted in mobile communications, consumer electronics, enterprises, and embedded systems. Nationally, we are capable of designing high-end memory semiconductors, but not in processors, resulting in unbalance. Generally, highly expensive software programs are necessary for designing processors which makes it difficult to set up proper environments. However, ModelSim simulator provided by Altera is free and everybody can use it. In this paper, the VHDL language which is widely used in Europe, universities, and research centers around the world for the ASIC design is selected for designing 32-bit ARM processor and simulated by ModelSim. As a result, 37 instructions of ARMv4 has been successfully executed.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.16 no.5
• /
• pp.191-196
• /
• 2016

Recently, power dissipation is a very significant issue not only in embedded systems and mobile devices but also in high-end modern processors. Especially, by the prevalent use of smart phones and tablet PCs, low power consumption of microprocessors is requisite. In this paper, a fast power measurement tool for a high performance microprocessor based on the trace-driven simulator has been developed. The power model of the microprocessor consists of complex combinational circuits, array structures, and CAM structures. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed to estimate the average power dissipation of each program.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.17 no.1
• /
• pp.219-224
• /
• 2017

Recently, the importance of DRAM is very significant not only in embedded systems and mobile devices but also in high-end modern microprocessors and multicore processors. To keep up with this, both industry and academia have actively studied various types of future DRAMs. Therefore, accurate DRAM model is requisite when evaluating the microprocessor performance. In this paper, a microprocessor trace-driven simulator which can couple with the cycle-accurate DRAM simulator has been developed. Using SPEC 2000 benchmarks as input, the effect of cycle-accurate DDR3 model on the microprocessor performance has been evaluated.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.8B
• /
• pp.755-761
• /
• 2004

Currently, Wireless LAN(WLAN) service is widely deployed to provide high speed wireless Internet access through the mobile stations such as notebook and PDA. To provide enhanced security and user access control in the public WLAN area, WLAM access points should have the capability of IEEE 802.1x-based user authentication and authorization functionality. In this paper, we provide a brief understanding of IEEE 802. 1x standards and related protocols likeEAPoL(Extended Authentication Protocol Over LAN), EAP, RADIUS and describe how the IEEE 802.1x is designed and implemented in our embedded linux-based WLAN AP which is named i-WiNG.(Intelligent Wireless Internet Gateway).

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.17 no.2
• /
• pp.251-256
• /
• 2017

Recently, multicore processor system is widely adopted not only in general purpose computers but also in embedded systems and mobile devices in order to improve performance. Since the power dissipation issue of multicore processor system is very significant, it must be estimated accurately in the early design stage. In this paper, a fast power analysis tool for a high performance multicore processor based on the trace-driven simulator has been developed. To achieve it, the power dissipation of each hardware unit per core are added. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed to estimate the average power dissipation per instruction.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
• /
• v.2
• /
• pp.391-394
• /
• 2006

The paper deals with the experimental GNSS receiver built at the Czech Technical University for experiments with the real GNSS signal. The receiver is based on software defined radio architecture. Receiver consists of the RF front end and a digital processor based on programmable logic. Receiver RF front end supports GPS L1, L2, L5, WAAS/EGNOS, GALILEO L1, E5A, E5B signals as well as GLONASS L1 and L2 signals. The digital processor is based on Field Programmable Gate Array (FPGA) which supports embedded processor. The receiver is used for various experiments with the GNSS signals like GPS L1/EGNOS receiver, GLONASS receiver and investigation of the EGNOS signal availability for a land mobile user. On the base of experimental GNSS receiver the GPS L1, L2, EGNOS receiver for railway application was designed. The experimental receiver is also used in GNSS monitoring station, which is independent monitoring facility providing also raw monitoring data of the GPS, EGNOS and Galileo systems via internet.

• Journal of Semiconductor Engineering
• /
• v.2 no.2
• /
• pp.130-135
• /
• 2021

Recently, deep neural networks (DNNs) are actively used for action control so that an autonomous system, such as the robot, can perform human-like behaviors and operations. Unlike recognition tasks, the real-time operation is essential in action control, and it is too slow to use remote learning on a server communicating through a network. New learning techniques, such as reinforcement learning (RL), are needed to determine and select the correct robot behavior locally. In this paper, we propose an energy-efficient DNN processor with a LUT-based processing engine and near-zero skipper. A CNN-based facial emotion recognition and an RNN-based emotional dialogue generation model is integrated for natural HRI system and tested with the proposed processor. It supports 1b to 16b variable weight bit precision with and 57.6% and 28.5% lower energy consumption than conventional MAC arithmetic units for 1b and 16b weight precision. Also, the near-zero skipper reduces 36% of MAC operation and consumes 28% lower energy consumption for facial emotion recognition tasks. Implemented in 65nm CMOS process, the proposed processor occupies 1784×1784 um2 areas and dissipates 0.28 mW and 34.4 mW at 1fps and 30fps facial emotion recognition tasks.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.42 no.5
• /
• pp.9-20
• /
• 2005

In this paper, we propose ubiTrack, a system which tracks users' location in indoor environments by employing infrared-based proximity method. Most of recently developed systems have focussed on performance and accuracy. For this reason, they adopted the idea of centralized management, which gathers all information in a main system to monitor users' location. However, these systems raise privacy concerns in ubiquitous computing environments where tons of sensors are seamlessly embedded into environments. In addition, centralized systems also need high computational power to support multiple users. The proposed ubiTrack is designed as a passive mobile architecture to relax privacy problems. Moreover, ubiTrack utilizes appropriate area as a unit to efficiently track users. To achieve this, ubiTrack overlaps each sensing area by utilizing the TDM (Time-Division Multiplexing) method. Additionally, ubiTrack exploits various filtering methods at each receiver and utilization module. The filtering methods minimize unexpected noise effect caused by external shock or intensity weakness of ID signal at the boundary of sensing area. ubiTrack can be applied not only to location-based applications but also to context-aware applications because of its associated module. This module is a part of middleware to support communication between heterogeneous applications or sensors in ubiquitous computing environments.