• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.742-745
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• 2004

If a personal robot is popularized like a personal computer in the future, many kinds of robots will appear and the number of manufacturers will increase as a matter of course. In such circumstances, it can be inefficient, in case each manufacturer makes a whole platform individually. The solutions for this problem are to modularize a robot component (hardware and software) functionally and to standardize each module. Each module is developed and sold by each special maker and a consumer purchases desired modules and integrates them. The standardization of a module includes the unification of electrical and mechanical interface. In this paper, the standard interfaces of modules are proposed and CMR(Component Modularized Robot)-P2 made with the modules(brain, sensor, mobile, arm) is introduced. In order to simplify and to make the modules light, a frame is used for supporting a robot and communication/power lines. The name of a method and the way to use that are defined dependently on the standard interfaces in order to use a module in other modules. Each module consists of a distributed object and that can be implemented in the random language and platform. The sensor, mobile and arm modules are developed on Pentium or ARM CPU and embedded Linux OS using the C programming language. The brain module is developed on Pentium CPU and Windows OS using the C, C++ and RPL(Robot Programming Language). Also tasks like pass planning, localization, moving, object perception and face perception are developed. In our test, modules got into gear and CMR-P2 executed various scenarios like guidance, errand and guarding completely.

• Journal of the Korea Computer Graphics Society
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• v.17 no.2
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• pp.37-43
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• 2011

OpenVG and SVG Tiny are the most widely used 2D vector graphics technologies for outputs in the various embedded environments including smart phones. Especially, to show high refresh rates on the high resolution screens, it is necessary to effectively accelerate them. Until now, OpenVG and SVG Tiny are available as hardware implementations such as the fully-dedicated graphics chips or full software implementations. Currently available vector graphics silicon chips are relatively expensive and require high power consumption. In contrast, previous full software implementations show lower performance even with almost 100% CPU usages, which would disrupt other multi-threaded applications, In this paper, we present a cost-effective way of accelerating both of OpenVG and SVG Tiny, based on the multimedia-processing hardware, which is wide-spread on the media devices and mobile phones. Through the effective use of these multimedia processors, we successfully accelerated OpenVG and SVG Tiny at least 3.5 times to at most 30 times, even with lower power consumption and lower CPU usage.

• KIPS Transactions on Computer and Communication Systems
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• v.9 no.10
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• pp.213-220
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• 2020

The power consumption and performance of hardware-based mobile and IoT embedded systems that require high specifications are one of the important issues of these systems. In particular, the problem of excessive power consumption is because it causes a problem of increasing heat generation and shortening the life of the device. In addition, in the same environment, software also needs to perform stable operation in limited power and memory, thereby increasing power consumption of the device. In order to solve these issues, we propose a Low level power improvement via identifying performance dissipation. The proposed method identifies complex modules (especially Cyclomatic complexity, Coupling & Cohesion) through code visualization, and helps to simplify low power code patterning and performance code. Therefore, through this method, it is possible to optimize the quality of the code by reducing power consumption and improving performance.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.6
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• pp.85-91
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• 2014

Nowadays, Dynamic lighting control and management skills are studied and used. If the system which is to manage multiple intelligent spot applied ubiquitous service technology is built with decision making and used in the complex intelligent space like a apartment then will improve energy efficiency and provide comfortability in optimal conditions. To solve this problem distributed autonomous control middleware and energy management system which process data gathering by zigbee mesh network and search proper services to save energy by the existing state of things is necessary. In paper we designed DDLEMS (Distributed Dynamic Lighting Energy Management System) that is to service duplex communication embedded by software based home server platform to provide mobile services in the smart place and support decision making about energy saving to the best use of wireless censor node and controled network, energy display devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.24-30
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• 2009

In this paper, the FPGA modem platform complying with 3GPP Release 7 eHSPA specifications and its regularized verification flow are proposed. The FFGA platform consists of modem board supporting physical layer requirements, MCU and DSP core embedded control board to drive the modem board, and peripheral boards for RF interfacing and various equipment interfaces. On the other hand, the proposed verification flow has been regularized into three categories according to the correlation degrees of hardware-software inter-operation, such as simple function test, scenario test call processing and system-level performance test. When it comes to real implementations, the emulation verification strategy for low power mobile SoC is also introduced.

• The Journal of the Korea Contents Association
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• v.6 no.12
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• pp.71-79
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• 2006

Recently, embedded systems like mobile and portable devices are quickly disseminated around the world. Since these.devices need more computation power as the applications become gradually complicated, the bettery lifetime becomes the most serious constraints. So research efforts have been focused on reducing the power consumption, resulting in producing devices with low-power H/W and S/W components. In this paper, we propose a low-power Java API set using the dynamic power management (DPM) scheme in the J2ME Java Platform on the real-time operating system UbiFOSTM and show that we could save energy up to 30% through experiments using the API set.

• Journal of the Korea Society of Computer and Information
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• v.15 no.8
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• pp.23-30
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• 2010

Flash memory is non-volatile and can retain data even after system is powered off. Besides, it has many other features such as fast access speed, low power consumption, attractive shock resistance, small size, and light-weight. As its price decreases and capacity increases, the flash memory is expected to be widely used in consumer electronics, embedded systems, and mobile devices. Flash storage systems generally adopt a software layer, called FTL. In this research, we proposed a new FTL mechanism for overcoming the major drawback of conventional block mapping algorithm. In addition to the block mapping table, a index block mapping table with a small size is used to indicate sector location. The proposed indexed block mapping algorithm by adding a small size. By the simulation result, the proposed FTL provides an enhanced speed than a conventional hybrid mapping algorithm by around 45% in average, and the requirement of mapping memory is also reduced by around 12%.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.5
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• pp.35-40
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• 2010

NAND flash memory has been widely used than traditional HDD in PDA and other mobile devices, embedded systems, PC because of faster access speed, low power consumption, vibration resistance and other benefits. DiskSim and other HDD simulators has been developed that for find improvements for the software or hardware. But there is a few Linux-based simulators for NAND flash memory and SSD. There is necessary for Windows-based NAND flash simulator because storage devices and PC using Windows. This paper describe for development of simulator-NFSim for FTL performance analysis in NAND flash. NFSim is used to measure performance of various FTL algorithms and FTL wear-level. NAND flash memory model and FTL algorithm developed using Windows Driver Model and class for scalability. There is no need for another tools because NFSim using graph tool for data measure of FTL performance.

• International Journal of Advanced Culture Technology
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• v.7 no.4
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• pp.313-320
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• 2019

Nowadays, as the availability of tiny, low-cost microcomputer increases at a high level, mobile robots are experiencing remarkable enhancements in hardware design, software performance, and connectivity advancements. In order to control Turtlebot 2, several algorithms have been developed using the Robot Operating System(ROS). However, ROS requires to be run on a high-cost computer which increases the hardware cost and the power consumption to the robot. Therefore, design an algorithm based on low-cost hardware is the most innovative way to reduce the unnecessary costs of the hardware, to increase the performance, and to decrease the power consumed by the computer on the robot. In this paper, we present a path-finding algorithm for TurtleBot 2 based on low-cost hardware. We implemented the algorithm using Raspberry pi, Windows 10 IoT core, and RPLIDAR A2. Firstly, we used Raspberry pi as the alternative to the computer employed to handle ROS and to control the robot. Raspberry pi has the advantages of reducing the hardware cost and the energy consumed by the computer on the robot. Secondly, using RPLIDAR A2 and Windows 10 IoT core which is running on Raspberry pi, we implemented the path-finding algorithm which allows TurtleBot 2 to navigate from the starting point to the destination using the map of the area. In addition, we used C# and Universal Windows Platform to implement the proposed algorithm.

• KIPS Transactions on Software and Data Engineering
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• v.9 no.5
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• pp.169-176
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• 2020

Recently, deep neural networks (DNNs) have brought revolutions to many mobile and embedded devices by providing human-level machine intelligence for various applications. However, high inference accuracy of such DNNs comes at high computational costs, and, hence, there have been significant efforts to reduce computational overheads of DNNs either by compressing off-the-shelf models or by designing a new small footprint DNN architecture tailored to resource constrained devices. One notable recent paradigm in designing small footprint DNN models is sharing parameters in several layers. However, in previous approaches, the parameter-sharing techniques have been applied to large deep networks, such as ResNet, that are known to have high redundancy. In this paper, we propose a parameter-sharing method for already parameter-efficient small networks such as ShuffleNetV2. In our approach, small templates are combined with small layer-specific parameters to generate weights. Our experiment results on ImageNet and CIFAR100 datasets show that our approach can reduce the size of parameters by 15%-35% of ShuffleNetV2 while achieving smaller drops in accuracies compared to previous parameter-sharing and pruning approaches. We further show that the proposed approach is efficient in terms of latency and energy consumption on modern embedded devices.