• 한국IT서비스학회지
• /
• 제18권4호
• /
• pp.171-190
• /
• 2019

This study comparatively analyzes the cases of CDMA (Code Division Multiple Access) and WIPI (Wireless Internet Platform for Interoperability) to find out the success and failure factors of technology policies in the field of mobile communication industry. For this purpose, the two cases are analyzed through a new analysis framework, which is made by combining System of Innovation with a range of variables derived from precedent studies, such as external environment, institutions, technological system, governance structure, and interactions of actors. The results of analysis show that in the CDMA case, the following factors led to success ; Korea made good use of the external opportunities in the early stage of digital communication technology and adopted a suitable governance structure for the technological system. Main actors in Innovation System had strong will for success and engaged in cooperative interaction. For the WIPI, however, the timing of technology policy was inappropriate and a unsuitable governance structure for technological system was chosen because of path dependence. The Innovation System failded to respond efficiently to the situation where conflicts among actors had intensified, US trade pressure had increased and innovative smartphones emerged. The results of this study provide the practical implications for the success of technology policy; namely it is important to choose a governance structure that suits the external environment and characteristics of technology and to activate cooperative interactions among actors in Innovation System.

• 산업공학
• /
• 제20권2호
• /
• pp.216-226
• /
• 2007

In code-division multiple-access (CDMA) systems with soft handoff, mobile station (MS) within soft handoff region can use multiple radio channels and receive their signals from multiple base stations (BSs) simultaneously. In this paper, the effects of soft handoff region ratio (SHRR) on reverse link of a CDMA cellular system are analytically investigated. In order to analyze the network performance and quality of service (QoS) perceived by users more realistically, both the soft capacity increasing factor and the traffic load variation affected by SHRR are jointly considered and a two-dimensional continuous time Markov chain (CTMC) model is built. In the numerical example, it is observed that the optimal guard channel exists according the variations of the traffic load and propagation conditions when the proper value of SHRR is determined.

• 한국정보통신학회:학술대회논문집
• /
• 한국해양정보통신학회 2004년도 춘계종합학술대회
• /
• pp.190-195
• /
• 2004

본 논문에서는 라이시안 페이딩 환경에서 길쌈 부호화된 DS-CDMA 16 QAM 신호의 선택 합성 다이버시티 수신기법 채용 및 최대비 합성 다이버시티 수신기법 채용시의 오율 성능을 해석한다. 해석 결과에 의하면 다이버시티 수신기법으로서 선택 합성 다이버시티 수신기법을 사용하는 것보다 최대비 합성 다이버시티 수신기법을 사용하는 것이 무선데이터 통신을 위한 오율 성능에서 약 3-8[㏈]의 성능 개선 효과가 있다. 또한 다이버시티 수신기법과 길쌈부호화 기법을 함께 채용하여 이동 무선 데이터 통신채널 환경을 극복할 수 있는 성능 개선 효과를 보인다.

• 한국정보통신학회논문지
• /
• 제13권10호
• /
• pp.2227-2234
• /
• 2009

이동체에 대해서 위성을 이용한 통신 방식을 규정하고 있는 DVB-SSP 표준화에서는 Physical Layer와 Upper Layer의 두 단계로 부호화 및 복호화를 한다. 수신단에서 Physical Layer의 복호 방식인 LDPC 복호 후 Upper Layer의 erasure RS 복호를 위해, CRC 검사를 수행하여 수신된 데이터에서 1 bit의 오류발생에도 IP 패킷 모두를 삭제함으로써 복호 시 비효율성을 증가시킬 수 있다. 따라서 본 논문에서는 LDPC 복호기에 출력되는 LLR 값을 이용하여 IP 패킷 전체를 삭제하는 것이 아니라 LLR 값이 낮은 비트만 선택적으로 삭제하는 방식을 제안하며, 이를 시뮬레이션 하여 기존의 CRC 방식과 비교하였다.

• 전기학회논문지
• /
• 제57권4호
• /
• pp.706-714
• /
• 2008

In this paper, we suggest a practical and flexible system architecture for JTAG(Joint Test Action Group) protection of application processors. From the view point of security, the debugging function through JTAG port can be abused by malicious users, so the internal structures and important information of application processors, and the sensitive information of devices connected to an application processor can be leak. This paper suggests a system architecture that disables computing power of computers used to attack processors to reveal important information. For this, a user authentication method is used to improve security strength by checking the integrity of boot code that is stored at boot memory, on booting time. Moreover for user authorization, we share hard wired secret key cryptography modules designed for functional operation instead of hardwired public key cryptography modules designed for only JTAG protection; this methodology allows developers to design application processors in a cost and power effective way. Our experiment shows that the security strength can be improved up to $2^{160}{\times}0.6$second when using 160-bit secure hash algorithm.

• 한국컴퓨터정보학회논문지
• /
• 제7권3호
• /
• pp.135-142
• /
• 2002

본 논문에서는 데이터 상관기들의 증가로 인한 데이터 처리시간 지연을 감소시키기 위해 Walsh Switch, 공유 accumulator, 그리고 파이프라인 FWHT 알고리즘을 적용한 새로운 Rake Finger 구조를 제안했다. 모의실험 결과, 왈쉬 코드 채널의 수 N＝4에 대한 데이터 상관기의 연산 동작 수는 512 additions에서 160 additions로 약 3.2배 감소하였고, Rake Finger의 데이터 처리시간은 110,696(ns)에서 90,496(ns)로 18.3% 감소하였음을 확인하였다.

• 한국정보통신학회:학술대회논문집
• /
• 한국정보통신학회 2014년도 추계학술대회
• /
• pp.363-365
• /
• 2014

스마트폰에서 인터넷뱅킹, 전자상거래, 업무의 처리 등 국민의 정치, 경제, 사회 실생활의 업무는 사이버 공간에서도 처리된다. 사이버 공간과 실제 공간의 경계가 모호해짐에 따라, 국가의 인프라 시설 관리 및 운영에서도 사이버 테러가 발생하고, 국가 안보위협의 가능성이 높아지고 있다. 국가의 주요 인프라 및 정부 서비스가 정보통신 시스템과 시설로 연계되어 있다. 사이버 테러와 국가 사이버안보에 관한 중대한 위협에 대처하기 위한 법과 제도적 장치로서, 국가사이버안보시스템에 관한 법률체계의 정립이 필요하다. 이를 위해 현재 국회에 계류 중인 사이버안보 관련법을 중심으로 분석과 현행 우리나라의 사이버 관련 법체계와 대별하여 분석하고, 국가사이버안보 컨트롤타워 문제와 국가사이버안보 인력 및 산업육성이 논의되어져야 하며, 사이버테러 대응 체계를 분석하여, 국가 사이버안보 시스템 관련 법률제정의 필요성을 연구한다.

• Nuclear Engineering and Technology
• /
• 제53권4호
• /
• pp.1167-1175
• /
• 2021

The process of automation and monitoring in industrial control system involves the use of many types of sensors. A programmable logic controller plays an important role in the automation of the different processes in the power plant system. The major control units are boiler for temperature and pressure, turbine for speed of motor, generator for voltage, conveyer belt for fuel. The power plant units are controlled using microcontrollers and PLCs, but FPGA can be the feasible solution. The paper focused on the design and simulation of hardware chip to monitor boiler, turbine, generator and conveyer belt. The hardware chip of the plant is designed in Xilinx Vivado Simulator 17.4 software using VHDL programming. The methodology includes VHDL code design, simulation, verification and testing on Virtex-5 FPGA hardware. The system has four independent buzzers used to indicate the status of the boiler, generator, turbine motor and conveyer belt in on/off conditions respectively. The GSM is used to display corresponding message on the mobile to know the status of the device in on/off condition. The system is very much helpful for the industries working on plant automation with FPGA hardware integration.

• ETRI Journal
• /
• 제45권2호
• /
• pp.318-328
• /
• 2023

Recently, embedded systems, such as mobile platforms, have multiple processing units that can operate in parallel, such as centralized processing units (CPUs) and neural processing units (NPUs). We can use deep-learning compilers to generate machine code optimized for these embedded systems from a deep neural network (DNN). However, the deep-learning compilers proposed so far generate codes that sequentially execute DNN operators on a single processing unit or parallel codes for graphic processing units (GPUs). In this study, we propose PartitionTuner, an operator scheduler for deep-learning compilers that supports multiple heterogeneous PUs including CPUs and NPUs. PartitionTuner can generate an operator-scheduling plan that uses all available PUs simultaneously to minimize overall DNN inference time. Operator scheduling is based on the analysis of DNN architecture and the performance profiles of individual and group operators measured on heterogeneous processing units. By the experiments for seven DNNs, PartitionTuner generates scheduling plans that perform 5.03% better than a static type-based operator-scheduling technique for SqueezeNet. In addition, PartitionTuner outperforms recent profiling-based operator-scheduling techniques for ResNet50, ResNet18, and SqueezeNet by 7.18%, 5.36%, and 2.73%, respectively.

• International Journal of Computer Science & Network Security
• /
• 제24권8호
• /
• pp.205-213
• /
• 2024

As the Restaurant industry is growing rapidly. The demand for an effortless POS (Point Of Sale) system which can make management easy is increasing. So, the purpose of this study is to digitalise the growing industry of restaurants and its consumers by utilizing cross-platform development. Crossplatform development frameworks provide great opportunities to solve the issues of handling ubiquitous devices with minimum efforts to reduce the cost and increase the stability, accessibility of the end consumers. By availing those opportunities, an Integrated POS system with cross platform is proposed. This integrated cross-platform POS system is originally designed for a single restaurant managed by its own private cloud server. This research solves the 2 major problems. One of them is the accessibility of the system on modern devices without even writing platform-specific code with the help of cross-platform development. This included web, mobile, desktops & tablets at the same time with the same codebase. Second one is handling data consistency with ubiquitous devices with the help of cloud infrastructure to make data safe and consistent more than ever. In the Development of this system Dart will be used as the primary programming language for cross-platform development. On the Cloud server system apache will be used as the web server and PHP as server side language. System will be using MySQL as the database server.